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参数资料
| 型号： | YF80532KC0211M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 54/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0211M |
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30
Datasheet
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50 V.
2.12
AGTL+ System Bus Specifications
Routing topologies are dependent on the number of processors supported and the chipset used in
the design. Please refer to the appropriate platform design guidelines. In most cases, termination
resistors are not required as these are integrated into the processor. See Table 5 for details on which
AGTL+ signals do not include on-die termination. The termination resistors are enabled or disabled
through the ODTEN pin. To enable termination, this pin should be pulled up to VCC through a
resistor and to disable termination, this pin should be pulled down to VSS through a resistor. For
optimum noise margin, all pull-up and pull-down resistor values used for the ODTEN pin should
have a resistance value within ± 20% of the impedance of the baseboard transmission line traces.
For example, if the trace impedance is 50
, then a value between 40 and 60 should be used.
The processor's on-die termination must be enabled for the end agent only. Please refer to Table 12
for termination resistor values. For more details on platform design see the appropriate platform
design guidelines.
Valid high and low levels are determined by the input buffers via comparing with a reference
voltage called GTLREF.
Table 12 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be
generated on the baseboard using high precision voltage divider circuits. It is important that the
baseboard impedance is held to the specified tolerance, and that the intrinsic trace capacitance for
the AGTL+ signal group traces is known and well-controlled. For more details on platform design
see the appropriate platform design guidelines.
Table 13. BSEL[1:0] and VID[4:0] DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
Ron (BSEL)
Buffer On
Resistance
9.2
14.3
2
Ron
(VID)
Buffer On
Resistance
7.8
12.8
2
IHI
Pin Leakage Hi
N/A
100
A
3
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