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参数资料
| 型号： | YF80532KC0211M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, CPGA603 |
| 封装： | MICRO, PGA-603 |
| 文件页数： | 23/129页 |
| 文件大小： | 1528K |
| 代理商： | YF80532KC0211M |
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Datasheet
119
BR0#
BR[1:3]#1
I/O
I
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual processor
pins. The tables below give the rotating interconnect between the processor and
bus signals for 2-way and 4-way systems.
During power-on configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition
of RESET#. The pin which the agent samples asserted determines it’s agent ID.
These signals do not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
BSEL[1:0]
O
BSEL[1:0] (Bus Select) output signals are used to select the system bus frequency.
A BSEL[1:0] = “00” will select a 100 MHz bus clock frequency. The frequency is
determined by the processor(s), chipset, and frequency synthesizer capabilities. All
system bus agents must operate at the same frequency. The Intel Xeon processor
MP on the 0.13 micron process processor currently operates at 100 MHz system
bus frequencies. Individual processors will only operate at their specified front side
bus (FSB) frequency.
On baseboards which support operation only at 100 MHz bus clocks these signals
can be ignored.
See the appropriate platform design guide for implementation examples.
page 18 for output values.
COMP[1:0]
I
COMP[1:0] must be terminated to VSS on the baseboard using precision resistors.
These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate
platform design guidelines and Table 14 for implementation details.
Table 52. Signal Definitions (Sheet 3 of 10)
Name
Type
Description
BR[1:0]# Signals Rotating Interconnect, 2-way system
BR2# and BR3# must not be utilized in 2-way platform designs.
BR[3:0]# Signals Rotating Interconnect, 4-way system (MP processors only)
Bus Signal
Agent 0 Pins Agent 1 Pins
Agent 2 pins
Agent 3 pins
BREQ0#
BR0#
BR3#
BR2#
BR1#
BREQ1#
BR1#
BR0#
BR3#
BR2#
BREQ2#
BR2#
BR1#
BR0#
BR3#
BREQ3#
BR3#
BR2#
BR1#
BR0#
Bus Signal
Agent 0 Pins Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
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