Intel
82865G/82865GV GMCH Datasheet
121
Register Description
3.8.15
SSTS3—Secondary Status Register (Device 3)
Address Offset:
Default Value:
Access:
Size:
1E–1Fh
02A0h
RO, RWC
16 bits
SSTS3 is a 16 bit status register that reports the occurrence of error conditions associated with the
secondary side (i.e., CSA side) of the virtual PCI-to-PCI bridge in the GMCH.
Note:
For R/WC bits, software must write a 1 to clear bits that are set.
Bit
Description
15
Detected Parity Error (DPE)— RO.
Hardwired to 0. Parity is not supported on the CSA interface.
14
Received System Error (RSE)—R/WC.
0 = No system error signalled by CSA device.
1 = CSA device signals a system error to the GMCH.
13
Received Master Abort Status (RMAS)
R/WC.
0 = No master abort by GMCH to terminate a Host-to-CSA transaction.
1 = GMCH terminated a Host-to-CSA transaction with an unexpected master abort.
12
Received Target Abort Status (RTAS)
R/WC.
0 = No target abort for GMCH-initiated transaction on CSA.
1 = GMCH-initiated transaction on CSA is terminated with a target abort.
11
Signaled Target Abort Status (STAS)—RO.
Hardwired to 0. The GMCH does not generate a
target abort on CSA.
10:9
DEVSEL# Timing (DEVT) —RO.
Hardwired to 01b. This 2-bit field indicates the timing of the
DEVSEL# signal when the GMCH responds as a target on CSA. The 01b value (medium timing)
indicates the time when a valid DEVSEL# can be sampled by initiator of the PCI cycle.
8
Master Data Parity Detected (DPD)—RO.
Hardwired to 0. GMCH does not implement G_PERR#
signal on CSA.
7
Fast Back-to-Back (FB2B)—RO.
Hardwired to 1. GMCH, as a target, supports fast back-to-back
transactions on CSA.
6
Reserved.
5
66/60 MHz PCI Capable (CAP66)—RO.
Hardwired to 1. CSA is 66 MHz capable.
4:0
Reserved.