Intel
82865G/82865GV GMCH Datasheet
83
Register Description
3
AGP Mode (AGP/DVO#)—RO.
This bit reflects the GPAR/ADD_DETECT# strap value. This strap
bit determines the function of the AGP I/O pins. Note that the strap value is sampled on the
assertion of PWROK.
0 = 2xDVO
1 = AGP
When the strap is sampled low, this bit will be a 0 and DVO mode will be selected. When the strap
is sampled high, this bit will be a 1 and AGP mode will be selected. In addition, this bit is forced to
1 if the AGP 3.0 detect bit (AGPSTAT.3) is 1. This is shown in the following table:
AGP 30_MOD bit
ADD_DETECT Strap
Resulting AGP/DVO#
0
0
0
1
1
x
0
1
1
NOTE:
When this bit is set to 0 (DVO Mode), AGP is disabled (configuration cycles fall-through
to HI) and the Next Pointer field in CAPREG in Device 0 will be hardwired to all 0s.
2
FSB IOQ Depth (IOQD)—RO.
This bit reflects the HA7# strap value. It indicates the depth of the
FSB IOQ. When the strap is sampled low, this bit will be a 0 and the FSB IOQ depth is set to 1.
When the strap is sampled high, this bit will be a 1 and the FSB IOQ depth is set to the maximum
(12 on the bus, 12 on the GMCH).
0 = 1 deep
1 = 12 on the bus, 12 on the GMCH
1:0
FSB Frequency Select (FSBFREQ)—RO.
The default value of this bit is set by the strap
assigned to the BSEL[1:0] pins and is latched at the rising edge of PWROK.
00 = Core Frequency is 100 MHz and the FSB frequency is 400 MHz
01 = Core Frequency is 133 MHz and the FSB frequency is 533 MHz
10 = Core Frequency is 200 MHz and the FSB frequency is 800 MHz
11 = Reserved
Bit
Descriptions