Intel
82865G/82865GV GMCH Datasheet
53
Register Description
3.4.1
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
Default Value:
Access:
Size:
0CF8h–0CFBh (Accessed as a DWord)
00000000h
R/W
32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DWord. A Byte or Word
reference will “pass through” the Configuration Address register and HI onto the PCI_A bus as an
I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function
Number, and Register Number for which a subsequent configuration access is intended.
Bit
Descriptions
31
Configuration Enable (CFGE).
1 = Enable
0 = Disable
30:24
Reserved. These bits are read only and have a value of 0.
23:16
Bus Number.
When the Bus Number is programmed to 00h, the target of the configuration cycle is
a HI agent (GMCH, ICH5, etc.).
The configuration cycle is forwarded to HI if the Bus Number is programmed to 00h and the GMCH
is not the target (i.e., the device number is not equal to 0, 1, 2, 3, 6 or 7).
If the Bus Number is non-zero and matches the value programmed into the Secondary Bus
Number register of Device 1, a Type 0 PCI configuration cycle will be generated on AGP/PCI_B.
If the Bus Number is non-zero, greater than the value in the Secondary Bus Number register of
Device 1 and less than or equal to the value programmed into the Subordinate Bus Number
register of Device 1, a Type 1 PCI configuration cycle will be generated on AGP/PCI_B.
If the Bus Number is non-zero, and does not fall within the ranges enumerated by Device 1’s
Secondary Bus Number or Subordinate Bus Number register, then a HI Type 1 configuration cycle
is generated.
15:11
Device Number.
This field selects one agent on the PCI bus selected by the Bus Number. When
the Bus Number field is 00, the GMCH decodes the Device Number field. The GMCH is always
Device Number 0 for the Host-HI bridge entity and Device Number 1 for the Host-PCI_B/AGP
entity. Therefore, when the Bus Number = 0 and the Device Number equals 0,1, 2, 3, 6, the
internal GMCH devices are selected.
If the Bus Number is non-zero and matches the value programmed into the Device1 Secondary
Bus Number register, a Type 0 PCI configuration cycle is generated on AGP/PCI_B. The Device
Number field is decoded and the GMCH asserts one and only one GADxx signal as an IDSEL.
GAD16 is asserted to access Device 0, GAD17 for Device 1, and so forth up to Device 15 for
which will assert AD31. All device numbers higher than 15 cause a type 0 configuration access
with no IDSEL asserted; this will result in a Master Abort reported in the GMCH’s virtual PCI-to-PCI
bridge registers.
For Bus Numbers resulting in HI configuration cycles, the GMCH propagates the Device Number
field as A[15:11]. For Bus Numbers resulting in AGP/PCI_B Type 1 configuration cycles, the
Device Number is propagated as GAD[15:11].
10:8
Function Number.
This field is mapped to GAD[10:8] during AGP/PCI_B configuration cycles and
A[10:8] during HI configuration cycles. This allows the configuration registers of a particular
function in a multi-function device to be accessed. The GMCH ignores configuration cycles to its
internal devices if the function number is not equal to 0.
7:2
Register Number.
This field selects one register within a particular bus, device, and function as
specified by the other fields in the Configuration Address register. This field is mapped to GAD[7:2]
during AGP/PCI_B Configuration cycles and A[7:2] during HI configuration cycles.
1:0
Reserved. These bits are read only.