Intel
82865G/82865GV GMCH Datasheet
157
Functional Description
5.2.6
Configuration Mechanism for DIMMS
Detection of the type of SDRAM installed on the DIMM is supported via the Serial Presence
Detect (SPD) mechanism as defined in the JEDEC DIMM specification. This uses the SCL, SDA,
and SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special
programmable modes are provided on the GMCH for detecting the size and type of memory
installed. Type and size detection must be accomplished via the serial presence detection pins and
is required to configure the GMCH.
5.2.6.1
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the GMCH SDRAM registers must be
initialized. The GMCH must be configured for operation with the installed memory types.
Detection of memory type and size is accomplished via the System Management Bus (SMBus)
interface on the ICH5. This two-wire bus is used to extract the SDRAM type and size information
from the Serial Presence Detect port on the SDRAM DIMMs. SDRAM DIMMs contain a 5-pin
Serial Presence Detect interface, including SCL (serial clock), SDA (serial data), and SA[2:0].
Devices on the SMBus bus have a 7-bit address. For the SDRAM DIMMs, the upper four bits are
fixed at 1010. The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected
to the System Management Bus on the ICH5. Thus, data is read from the Serial Presence Detect
port on the DIMMs via a series of I/O cycles to the ICH5. BIOS needs to determine the size and
type of memory used for each of the rows of memory to properly configure the GMCH memory
interface.
5.2.6.2
SMBus Configuration and Access of the Serial Presence
Detect Ports
For more details, refer to the
Intel
82801EB I/O Controller Hub 5 (ICH5) and Intel
82801ER
I/O Controller Hub 5R (ICH5R) Datasheet
.
5.2.6.3
Memory Register Programming
This section provides an overview of how the required information for programming the SDRAM
registers is obtained from the Serial Presence Detect ports on the DIMMs. The Serial Presence
Detect ports are used to determine Refresh Rate, SMA and SMD Buffer Strength, Row Type (on a
row-by-row basis), SDRAM Timings, Row Sizes, and Row Page Sizes.
Table 26
lists a subset of
the data available through the on board Serial Presence Detect ROM on each DIMM.
Table 26. Data Bytes on DIMM Used for Programming DRAM Registers
Byte
Function
2
Memory type (DDR SDRAM)
3
Number of row addresses, not counting bank addresses
4
number of column addresses
5
Number of banks of SDRAM (single- or double-sided DIMM)
11
ECC, non-ECC (865G chipset GMCH does not support ECC)
12
Refresh rate
17
Number of banks on each device