26
Intel
82865G/82865GV GMCH Datasheet
Signal Description
Figure 2. Intel
82865G GMCH Interface Block Diagram
SCS_A[3:0]#
SMAA_A[12:0], SMAB_A[5:1]
SBA_A[1:0]
SRAS_A#
SCAS_A#
SWE_A#
SDQ_A[63:0]
SDM_A[7:0]
SDQS_A[8:0]
SCKE_A[3:0]
SCMDCLK_A[5:0], SCMDCLK_A[5:0]#
AGP
Interface
(multiplexed
with DVO)
GSBA[7:0]
GPIPE#
GST[2:0]
GRBF#
GWBF#
GADSTB[1:0], GADSTB[1:0]#
GSBSTB, GSBSTB#
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GREQ#
GGNT#
GAD[31:0]
GC/BE[3:0]#
GPAR/ADD_DETECT
—
Processor
System
Bus
Interface
HA[31:3]#
HD[63:0]#
ADS#
BNR#
BPRI#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
CPURST#
BREQ0#
DINV[3:0]#
HADSTB[1:0]#
HDSTBP[3:0]#, HDSTBN[3:0]#
System
Memory
DDR
Channel
A
Hub
Interface
HI[10:0]
HISTRS
HISTRF
HDVREF
HDRCOMP
HDSWING
SMVREF_A, SMVREF_B
SMXRCOMPVOL, SMYRCOMPVOL
SMXRCOMPVOH, SMYRCOMPVOH
SMXRCOMP, SMYRCOMP
GVREF
GVSWING
GRCOMP/DVOBCRCOMP
HI_VREF
HI_RCOMP
HI_SWING
CI_VREF
CI_RCOMP
CI_SWING
VCC
VSS
VCCA_AGP
VCC_AGP
VCCA_FSB
VTT
VCCA_DPLL
VCC_DAC
VCCA_DAC
VSSA_DAC
VCC_DDR
VCCA_DDR
Voltage
Refernce,
RCOMP,
VSWING,
and Power
DVO Device
Interface
DVOB_CLK, DVOB_CLK#
DVOB_D[11:0]
DVOB_HSYNC
DVOB_VSYNC
DVOB_BLANK#
DVOBC_CLKINT
DVOB_FLDSTL
DVOC_CLK, DVOC_CLK#
DVOC_D[11:0]
DVOC_HSYNC
DVOC_VSYNC
DVOC_BLANK#
DVOBC_INTR#
DVOC_FLDSTL
MI2C_CLK
MI2C_DATA
MDVI_CLK
MDVI_DATA
MDDC_CLK
MDDC_DATA
ADDID[7:0]
HCLKP, HCLKN
GCLKIN
DREFCLK
RSTIN#
PWROK
EXTTS#
TESTIN#
Clocks,
Reset, &
Test
Analog
Display
HSYNC
VSYNC
RED, RED#
GREEN, GREEN#
BLUE, BLUE#
REFSET
DDCA_CLK
DDCA_DATA
SCS_B[3:0]#
SMAA_B[12:0], SMAB_B[5:1]
SBA_B[1:0]
SRAS_B#
SCAS_B#
SWE_B#
SDQ_B[63:0]
SDM_B[7:0]
SDQS_B[8:0]
SCKE_B[3:0]
SCMDCLK_B[5:0], SCMDCLK_B[5:0]#
System
Memory
DDR
Channel
B
CSA
Interface
CI[10:0]
CISTRS
CISTRF
AGP 3.0
AGP 2.0
GSBA[7:0]#
DBI_HI
GST[2:0]
GRBF
GWBF
GADSTBF[1:0], GADSTBS[1:0]
GSBSTBF, GSBSTBS
GFRAME
GIRDY
GTRDY
GSTOP
GDEVSEL
GREQ
GGNT
GAD[31:0]
GC#/BE[3:0]
GPAR/ADD_DETECT
DBI_LO (3.0 only)
(multiplexed
with AGP)