58
Intel
82865G/82865GV GMCH Datasheet
Register Description
3.5.3
PCICMD—PCI Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
04–05h
0006h
RO, R/W
16 bits
Since GMCH Device 0 does not physically reside on PCI_A, many of the bits are not implemented.
Writes to non-implemented bits have no effect.
Bit
Descriptions
15:10
Reserved.
9
Fast Back-to-Back Enable (FB2B)—RO.
Hardwired to 0. This bit controls whether or not the
master can do fast back-to-back writes. Since Device 0 is strictly a target, this bit is not
implemented and is hardwired to 0.
8
SERR Enable (SERRE)—R/W.
This bit is a global enable bit for Device 0 SERR messaging. The
GMCH does not have a SERR signal. The GMCH communicates the SERR condition by sending a
SERR message over HI to the ICH5.
0 = Disable. The SERR message is not generated by the GMCH for Device 0. Note that this bit
only controls SERR messaging for the Device 0. Device 1 has its own SERRE bits to control
error reporting for error conditions occurring on their respective devices. The control bits are
used in a logical OR manner to enable the SERR HI message mechanism.
1 = Enable. The GMCH is enabled to generate SERR messages over HI for specific Device 0
error conditions that are individually enabled in the ERRCMD register. The error status is
reported in the ERRSTS and PCISTS registers.
7
Address/Data Stepping Enable (ADSTEP)—RO.
Hardwired to 0.
6
Parity Error Enable (PERRE)—RO.
Hardwired to 0. The PERR# signal is not implemented by the
GMCH.
5
VGA Palette Snoop Enable (VGASNOOP)—RO.
Hardwired to 0.
4
Memory Write and Invalidate Enable (MWIE)—RO.
Hardwired to 0. The GMCH will never issue
memory write and invalidate commands.
3
Special Cycle Enable (SCE)—RO.
Not implemented; hardwired to 0.
2
Bus Master Enable (BME)—RO.
Hardwired to 1. GMCH is always enabled as a master on HI.
1
Memory Access Enable (MAE)—RO.
Hardwired to 1. The GMCH always allows access to main
memory.
0
I/O Access Enable (IOAE)—RO.
Hardwired to 0.