Intel
82865G/82865GV GMCH Datasheet
77
Register Description
3.5.25
AGPCTRL—AGP Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
B0–B3h
00000000h
RO
,
R/W
32 bits
This register provides for additional control of the AGP interface.
Bit
Descriptions
31:8
Reserved.
7
GTLB Enable (GTLBEN)— R/W.
0 = Disable (default). The GTLB is flushed by clearing the valid bits associated with each entry. In
this mode of operation:
— All accesses that require translation bypass the GTLB
— All requests that are positively decoded to the graphics aperture force the GMCH to access
the translation table in main memory before completing the request
— Valid translation table entry fetches will not be cached in the GTLB
— Invalid translation table entry fetches will still be cached in the GTLB (ejecting the least
recently used entry).
1 = Enable. Normal operations of the Graphics Translation Lookaside Buffer are enabled.
NOTE:
This bit can be changed dynamically (i.e., while an access to GTLB occurs); however, the
completion of the configuration write that asserts or deasserts this bit will be delayed
pending a complete flush of all dirty entries from the write buffer. This delay will be
incurred because this bit is used as a mechanism to signal the chipset that the graphics
aperture translation table is about to be modified or has completed modifications. In the
first case, all dirty entries need to be flushed before the translation table is changed. In the
second case, all dirty entries need to be flushed because one of them is likely to be a
translation table entry which must be made visible to the GTLB by flushing it to memory.
6:1
Reserved.
0
4X Override (OVER4X)—R/W.
This back-door register bit allows the BIOS to force 1X mode for
AGP 2.0 and 4X mode for AGP 3.0. Note that this bit must be set by the BIOS before AGP
configuration.
0 = No override
1 = The RATE[2:0] bit in the AGPSTS register will be read as a 001.