134
Intel
82865G/82865GV GMCH Datasheet
Register Description
3.10.2
DRA—DRAM Row Attribute Register (Device 6, MMR)
Address Offset:
Default Value:
Access:
Size:
0010h–0013h
00h
RO, R/W
8 bits each register
The DRAM Row Attribute registers define the page sizes to be used when accessing different rows
or pairs of rows. The minimum page size of 4 KB occurs when in single-channel mode and either
128-Mb, x16 devices are populated or 256-Mb, x16 devices are populated. The maximum page
size of 32 KB occurs when in dual-channel mode and 512-MB, x8 devices are populated. Each
nibble of information in the DRA registers describes the page size of a row or pair of rows. When
in either of the dual-channel modes, only registers 10h and 11h are used. The page size
programmed reflects the page size for the pair of DIMMS installed. When in single-channel mode,
registers 10h and 11h are used to specify page sizes for channel A and registers 12h and 13h are
used to specify page sizes for channel B.
If the associated row is not populated, the field must
be left at the default value.
Row0, 1:0010h
Row2, 3:0011h
Row4, 5:0012h
Row6, 7:0013h
7
6
4
3
2
0
Rsvd
Row Attribute for Row 1
Rsvd
Row Attribute for Row 0
7
6
4
3
2
0
Rsvd
Row Attribute for Row 3
Rsvd
Row Attribute for Row 2
7
6
4
3
2
0
Rsvd
Row Attribute for Row 5
Rsvd
Row Attribute for Row 4
7
6
4
3
2
0
Rsvd
Row Attribute for Row 7
Rsvd
Row Attribute for Row 6
Bit
Description
7
Reserved.
6:4
Row Attribute for Odd-Numbered Row—R/W.
This field defines the page size of the corresponding
row. If the associated row is not populated, this field must be left at the default value.
000 = 4 KB
001 = 8 KB
010 = 16 KB
011 = 32 KB
Others = Reserved
3
Reserved.
2:0
Row Attribute for Even-Numbered Row—R/W.
This field defines the page size of the corresponding
row. If the associated row is not populated, this field must be left at the default value.
000 = 4 KB
001 = 8 KB
010 = 16 KB
011 = 32 KB
Others = Reserved