Intel
82865G/82865GV GMCH Datasheet
213
Testability
8.2
XOR Chain Definition
The GMCH has 10 XOR chains. The XOR chain outputs are driven out on the output pins as
shown in
Table 43
. During fullwidth testing, XOR chain outputs will be visible on both pins
(For example, xor_out0 will be visible on SDM_A0 and SDM_B0). During channel shared mode
on the tester, outputs will be visible on their respective channels. (For example, in channel A mode,
xor_out0 will be visible on SDM_A0 and the same will be visible on SDM_B0 in channel B
mode.)
The following tables show the XOR chain pin mappings and their monitors for the GMCH.
Note:
Notes for
Table 44
through
Table 54
.
1. Only AGP differential strobes are on different chains but in the same channel group. Other
interface strobes are on the same chain since they are not required to be in opposite polarity all
the time. All XOR chains can be run in parallel, except chains with AGP strobes (chains 0 and
1, chains 0 and 2, and chains 2 and 4).
2. The channel A and channel B output pins for each chain show the same output.
3. For the multiplexed AGP and DVO signals, only the AGP signal names are listed. Refer to
Section 2.5.7
for the DVO-to-AGP signal mapping.
4. For AGP signals, only the AGP 3.0 signal name is listed. For the corresponding AGP 2.0
signal name, refer to
Chapter 2
.
Table 43. XOR Chain Outputs
XOR Chain
DDR Output Pin Channel A
DDR Output Pin Channel B
xor_out0
SDM_A0
SDM_B0
xor_out1
SDM_A1
SDM_B1
xor_out2
SDM_A2
SDM_B2
xor_out3
SDM_A3
SDM_B3
xor_out4
SDM_A4
SDM_B4
xor_out5
SDM_A5
SDM_B5
xor_out6
SDM_A6
SDM_B6
xor_out7
SDM_A7
SDM_B7
xor_out8
HTRDY#
BPRI#
xor_out9
RS2#
DEFER#
xor_out10
RS0#
RS1#
xor_out11
BREQ0#
CPURST#