Intel
82865G/82865GV GMCH Datasheet
79
Register Description
3.5.28
AMTT—AGP MTT Control Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
BCh
10h
RO, R/W
8 bits
AMTT is an 8-bit register that controls the amount of time that the GMCH’s arbiter allows AGP/
PCI master to perform multiple back-to-back transactions. The GMCH's AMTT mechanism is used
to optimize the performance of the AGP master (using PCI semantics) that performs multiple back-
to-back transactions to fragmented memory ranges (and as a consequence it can not use long burst
transfers). The AMTT mechanism applies to the Processor-AGP/PCI transactions as well and it
assures the processor of a fair share of the AGP/PCI interface bandwidth.
The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in
66 MHz clocks) allotted to the current agent (either AGP/PCI master or Host bridge) after which
the AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and disables
this function. The AMTT value can be programmed with 8-clock granularity. For example, if the
AMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP
(66 MHz) clocks. Set by BIOS.
Bit
Descriptions
7:3
Multi-Transaction Timer Count Value (MTTC)—R/W.
The number programmed into these bits
represents the time slice (measured in eight, 66 MHz clock granularity) allotted to the current agent
(either AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to another
agent.
2:0
Reserved.