参数资料
| 型号： | AD9557BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/92页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK TRANSLATOR 40LFCSP |
| 产品变化通告： | Minor Mask Change 11/Apr/2012 |
| 标准包装： | 1 |
| 类型： | 时钟/频率转换器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.25GHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页
Data Sheet
AD9557
Rev. B | Page 33 of 92
SYSTEM CLOCK (SYSCLK)
SYSTEM CLOCK INPUTS
Functional Description
The SYSCLK circuit provides a low jitter, stable, high frequency
clock for use by the rest of the chip. The XOA and XOB pins
connect to the internal SYSCLK multiplier. The SYSCLK multiplier
can synthesize the system clock by connecting a crystal resonator
across the XOA and XOB input pins or by connecting a low
frequency clock source. The optimal signal for the system clock
input is either a crystal in the 50 MHz range or an ac-coupled
square wave with a 1 V p-p amplitude.
System Clock Period
For the AD9557 to accurately measure the frequency of incoming
reference signals, the user must enter the system clock period
into the nominal system clock period registers (Register 0x0103
to Register 0x0105). The SYSCLK period is entered in units of
nanoseconds (ns).
System Clock Details
There are two internal paths for the SYSCLK input signal: low
frequency non-xtal (LF) and crystal resonator (XTAL).
Using a TCXO for the system clock is a common use for the
LF path. Applications requiring DPLL loop bandwidths of less
than 50 Hz or high stability in holdover require a TCXO. As an
alternative to the 49.152 MHz crystal for these applications, the
AD9557 reference design uses a 19.2 MHz TCXO, which offers
excellent holdover stability and a good combination of low jitter
and low spurious content.
The 1.8 V differential receiver connected to the XOA and XOB pins
is self-biased to a dc level of ~1 V, and ac coupling is strongly
recommended. When a 3.3 V CMOS oscillator is in use, it is
important to use a voltage divider to reduce the input high voltage
to a maximum of 1.8 V. See Figure 34 for details on connecting
a 3.3 V CMOS TCXO to the system clock input.
The non-xtal input path permits the user to provide an LVPECL,
LVDS, 1.8 V CMOS, or sinusoidal low frequency clock for
multiplication by the integrated SYSCLK PLL. The LF path
handles input frequencies from 3.5 MHz up to 100 MHz.
However, when using a sinusoidal input signal, it is best to use
a frequency that is in excess of 20 MHz. Otherwise, the resulting
low slew rate can lead to substandard noise performance. Note
that the non-xtal path includes an optional 2× frequency multiplier
to double the rate at the input to the SYSCLK PLL and potentially
reduce the PLL in-band noise. However, to avoid exceeding the
maximum PFD rate of 150 MHz, the 2× frequency multiplier is
only for input frequencies that are below 75 MHz.
The non-xtal path also includes an input divider (M) that is
programmable for divide-by-1, -2, -4, or -8. The purpose of
the divider is to limit the frequency at the input to the PLL to
less than 150 MHz (the maximum PFD rate).
The XTAL path enables the connection of a crystal resonator
(typically 10 MHz to 50 MHz) across the XOA and XOB pins.
An internal amplifier provides the negative resistance required
to induce oscillation. The internal amplifier expects an AT cut,
fundamental mode crystal with a maximum motional resistance
of 100 Ω. The following crystals, listed in alphabetical order, may
meet these criteria. Analog Devices, Inc., does not guarantee their
operation with the AD9557, nor does Analog Devices endorse one
crystal supplier over another. The AD9557 reference design uses
a 49.152 MHz crystal, which is high performance, low spurious
content, and readily available.
AVX/Kyocera CX3225SB
ECS ECX-32
Epson/Toyocom TSX-3225
Fox FX3225BS
NDK NX3225SA
Siward SX-3225
Suntsu SCM10B48-49.152 MHz
SYSTEM CLOCK MULTIPLIER
The SYSCLK PLL multiplier is an integer-N design with an
integrated VCO. It provides a means to convert a low frequency
clock input to the desired system clock frequency, fSYS (750 MHz
to 805 MHz). The SYSCLK PLL multiplier accepts input signals
of between 3.5 MHz and 600 MHz, but frequencies that are in
excess of 150 MHz require the system clock P-divider to ensure
compliance with the maximum PFD rate (150 MHz). The PLL
contains a feedback divider (N) that is programmable for divide
values between 4 and 255.
Pdiv
sysclk
Ndiv
sysclk
f
OSC
SYS
_
×
=
where:
fOSC is the frequency at the XOA and XOB pins.
sysclk_Ndiv is the value stored in Register 0x0100.
sysclk_Pdiv is the system clock P divider that is determined by the
setting of Register 0x0101[2:1].
If the system clock doubler is used, the value of sysclk_Ndiv
should be half of its original value.
The system clock multiplier features a simple lock detector that
compares the time difference between the reference and feedback
edges. The most common cause of the SYSCLK multiplier not
locking is a non-50% duty cycle at the SYSCLK input while the
system clock doubler is enabled.
相关PDF资料 |
PDF描述 |
|---|---|
| V375C36M150BG | CONVERTER MOD DC/DC 36V 150W |
| AD9547BCPZ | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| D38999/20MF11JN | CONN RCPT 11POS WALL MNT W/SCKT |
| AD9549ABCPZ | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| ADN2814ACPZ | IC CLOCK/DATA RECOVERY 32LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9557BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 40LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| AD9558 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad Input Multiservice Line Card Adaptive |
| AD9558/PCBZ | 功能描述:BOARD EVAL FOR AD9558 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:* 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9558BCPZ | 功能描述:IC CLOCK TRANSLATOR 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1 系列:- 类型:时钟/频率发生器，多路复用器 PLL:是 主要目的:存储器，RDRAM 输入:晶体 输出:LVCMOS 电路数:1 比率 - 输入:输出:1:2 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:Digi-Reel® 其它名称:296-6719-6 |
| AD9558BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
发布紧急采购，3分钟左右您将得到回复。