参数资料
| 型号： | AD9557BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 85/92页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK TRANSLATOR 40LFCSP |
| 产品变化通告： | Minor Mask Change 11/Apr/2012 |
| 标准包装： | 1 |
| 类型： | 时钟/频率转换器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.25GHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
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AD9557
Data Sheet
Rev. B | Page 86 of 92
Table 109. Digital PLL Lock Detect Tub Levels
Address
Bits
Bit Name
Description
0x0D11
[7:0]
Phase tub
Read-only digital PLL lock detect bathtub level[7:0] (see the DPLL Frequency Lock Detector section).
0x0D12
[7:4]
Reserved.
[3:0]
Read-only digital PLL lock detect bathtub level[11:8] (see the DPLL Frequency Lock Detector section).
0x0D13
[7:0]
Frequency tub
Read-only digital PLL lock detect bathtub level[7:0] (see the DPLL Phase Lock Detector section).
0x0D14
[7:4]
Reserved
Reserved.
[3:0]
Frequency tub
Read-only digital PLL lock detect bathtub level[11:8] (see the DPLL Phase Lock Detector section).
EEPROM CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E3C)
Table 110. EEPROM Control
Address
Bits
Bit Name
Description
0x0E00
[7:1]
Reserved
Reserved.
0
Write enable
EEPROM write enable/protect.
0 (default) = EEPROM write protected
1 = EEPROM write enabled.
0x0E01
[7:4]
Reserved
Reserved.
[3:0]
Conditional value
When set to a non-zero value, establishes the condition for EEPROM downloads. Default: 0.
0x0E02
[7:1]
Reserved
Reserved.
0
Save to EEPROM
Uploads data to the EEPROM (see the EEPROM Storage Sequence (Register 0X0E10 to Register
0X0E3C) section).
0x0E03
[7:2]
Reserved
Reserved.
1
Load from EPROM
Downloads data from the EEPROM.
0
Reserved
Reserved.
EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3C)
The default settings of Register 0x0E10 to Register 0x0E3C contain the default EEPROM instruction sequence. The tables in this section
provide descriptions of the register defaults, assuming that the controller has been instructed to carry out an EEPROM storage sequence
in which all of the registers are stored and loaded by the EEPROM.
Table 111. EEPROM Storage Sequence for System Clock Settings
Address
Bits
Bit Name
Description
0x0E10
[7:0]
EEPROM ID
The default value of this register is 0x01, which the controller interprets as a data instruction. Its
decimal value is 1, so this tells the controller to transfer two bytes of data (1 + 1), beginning at the
address specified by the next two bytes. The controller stores 0x01 in the EEPROM and increments
the EEPROM address pointer.
0x0E11
[7:0]
The default value of these two registers is 0x0006. Note that Register 0x0E11 and Register 0x0E12
are the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registers define a starting address (in this
case, 0x0006). The controller stores 0x0006 in the EEPROM and increments the EEPROM pointer by 2.
It then transfers two bytes from the register map (beginning at Address 0x0006) to the EEPROM
and increments the EEPROM address pointer by 3 (two data bytes and one checksum byte). The
two bytes transferred correspond to the system clock parameters in the register map.
0x0E12
[7:0]
0x0E13
[7:0]
System clock
The default value of this register is 0x08, which the controller interprets as a data instruction. Its
decimal value is 8, so this tells the controller to transfer nine bytes of data (8 + 1), beginning at the
address specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments
the EEPROM address pointer.
0x0E14
[7:0]
The default value of these two registers is 0x0100. Note that Register 0x0E14 and Register 0x0E15
are the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registers define a starting address (in this
case, 0x0100). The controller stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2.
It then transfers nine bytes from the register map (beginning at Address 0x0100) to the EEPROM
and increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The
nine bytes transferred correspond to the system clock parameters in the register map.
0x0E15
[7:0]
0x0E16
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O update instruction.
The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
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