参数资料
| 型号： | AD9557BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 86/92页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK TRANSLATOR 40LFCSP |
| 产品变化通告： | Minor Mask Change 11/Apr/2012 |
| 标准包装： | 1 |
| 类型： | 时钟/频率转换器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.25GHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
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Data Sheet
AD9557
Rev. B | Page 87 of 92
Table 112. EEPROM Storage Sequence for General Configuration Settings
Address
Bits
Bit Name
Description
0x0E17
[7:0]
General
The default value of this register is 0x11, which the controller interprets as a data
instruction. Its decimal value is 17, so this tells the controller to transfer 18 bytes of data
(17 + 1), beginning at the address specified by the next two bytes. The controller stores
0x11 in the EEPROM and increments the EEPROM address pointer.
0x0E18
[7:0]
The default value of these two registers is 0x0200. Note that Register 0x0E18 and
Register 0x0E19 are the most significant and least significant bytes of the target address,
respectively. Because the previous register contains a data instruction, these two
registers define a starting address (in this case, 0x0200). The controller stores 0x0200 in
the EEPROM and increments the EEPROM pointer by 2. It then transfers 18 bytes from
the register map (beginning at Address 0x0200) to the EEPROM and increments the
EEPROM address pointer by 19 (18 data bytes and one checksum byte). The 18 bytes
transferred correspond to the general configuration parameters in the register map.
0x0E19
[7:0]
Table 113. EEPROM Storage Sequence for DPLL Settings
Address
Bits
Bit Name
Description
0x0E1A
[7:0]
DPLL
The default value of this register is 0x2E, which the controller interprets as a data
instruction. Its decimal value is 46, so this tells the controller to transfer 47 bytes of data
(46 + 1), beginning at the address specified by the next two bytes. The controller stores
0x2E in the EEPROM and increments the EEPROM address pointer.
0x0E1B
[7:0]
The default value of these two registers is 0x03. Note that Register 0x0E1B and
Register 0x0E1C are the most significant and least significant bytes of the target address,
respectively. Because the previous register contains a data instruction, these two
registers define a starting address (in this case, 0x0300). The controller stores 0x0300 in
the EEPROM and increments the EEPROM pointer by 2. It then transfers 47 bytes from
the register map (beginning at Address 0x0300) to the EEPROM and increments the
EEPROM address pointer by 48 (47 data bytes and one checksum byte). The 47 bytes
transferred correspond to the DPLL parameters in the register map.
0x0E1C
[7:0]
Table 114. EEPROM Storage Sequence for APLL Settings
Address
Bits
Bit Name
Description
0x0E1D
[7:0]
APLL
The default value of this register is 0x08, which the controller interprets as a data instruction.
Its decimal value is 8, so this tells the controller to transfer nine bytes of data (8 + 1),
beginning at the address specified by the next two bytes. The controller stores 0x08 in
the EEPROM and increments the EEPROM address pointer.
0x0E1E
[7:0]
The default value of these two registers is 0x0400. Note that Register 0x0E1E and
Register 0x0E1F are the most significant and least significant bytes of the target address,
respectively. Because the previous register contains a data instruction, these two registers
define a starting address (in this case, 0x0400). The controller stores 0x0400 in the EEPROM
and increments the EEPROM pointer by 2. It then transfers nine bytes from the register
map (beginning at Address 0x0400) to the EEPROM and increments the EEPROM address
pointer by 10 (nine data bytes and one checksum byte). The nine bytes transferred
correspond to APLL parameters in the register map.
0x0E1F
[7:0]
Table 115. EEPROM Storage Sequence for Clock Distribution Settings
Address
Bits
Bit Name
Description
0x0E20
[7:0]
Clock distribution
The default value of this register is 0x15, which the controller interprets as a data instruction.
Its decimal value is 21, so this tells the controller to transfer 22 bytes of data (21+1),
beginning at the address specified by the next two bytes. The controller stores 0x15 in
the EEPROM and increments the EEPROM address pointer.
0x0E21
[7:0]
The default value of these two registers is 0x0500. Note that Register 0x0E21 and
Register 0x0E22 are the most significant and least significant bytes of the target address,
respectively. Because the previous register contains a data instruction, these two registers
define a starting address (in this case, 0x0500). The controller stores 0x0500 in the EEPROM
and increments the EEPROM pointer by 2. It then transfers 22 bytes from the register map
(beginning at Address 0x0500) to the EEPROM and increments the EEPROM address
pointer by 23 (22 data bytes and one checksum byte). The 22 bytes transferred correspond to
the clock distribution parameters in the register map.
0x0E22
[7:0]
0x0E23
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O update
instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address
pointer.
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