参数资料
| 型号： | AD9557BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 44/92页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK TRANSLATOR 40LFCSP |
| 产品变化通告： | Minor Mask Change 11/Apr/2012 |
| 标准包装： | 1 |
| 类型： | 时钟/频率转换器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.25GHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
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Data Sheet
AD9557
Rev. B | Page 49 of 92
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/
A
WE
A
bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
for data to be read from or written to it. If the R/
A
WE
A
bit is 0, the
master (transmitter) writes to the slave device (receiver). If the
R/
A
WE
A
bit is 1, the master (receiver) reads from the slave device
(transmitter).
The format for these commands is described in the Data
Transfer Format section.
Data is then sent over the serial bus in the format of nine clock
pulses: one data byte (eight bits) from either master (write mode)
or slave (read mode) followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted
per transfer is unrestricted. In write mode, the first two data
bytes immediately after the slave address byte are the internal
memory (control registers) address bytes, with the high address
byte first. This addressing scheme gives a memory address of up
to 216 1 = 65,535. The data bytes after these two memory
address bytes are register data written to or read from the
control registers. In read mode, the data bytes after the slave
address byte are register data written to or read from the control
registers.
When all data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a
stop condition to end data transfer during the 10th clock pulse
following the acknowledge bit for the last data byte from the
slave device (receiver). In read mode, the master device
(receiver) receives the last data byte from the slave device
(transmitter) but does not pull SDA low during the ninth clock
pulse. This is known as a nonacknowledge bit. By receiving the
nonacknowledge bit, the slave device knows that the data
transfer is finished and enters idle mode. The master then takes
the data line low during the low period before the 10th clock
pulse, and high during the 10th clock pulse to assert a stop
condition.
A start condition can be used in place of a stop condition.
Furthermore, a start or stop condition can occur at any time,
and partially transferred bytes are discarded.
12
89
12
3TO 7
89
10
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
SDA
SCL
S
MSB
P
09197-
038
Figure 52. Data Transfer Process (Master Write Mode, 2-Byte Transfer)
12
89
12
3TO 7
89
10
ACK FROM
MASTER RECEIVER
NON-ACK FROM
MASTER RECEIVER
SDA
SCL
S
P
09
19
7-
0
39
Figure 53. Data Transfer Process (Master Read Mode, 2-Byte Transfer)
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