参数资料
| 型号： | AD9557BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/92页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK TRANSLATOR 40LFCSP |
| 产品变化通告： | Minor Mask Change 11/Apr/2012 |
| 标准包装： | 1 |
| 类型： | 时钟/频率转换器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.25GHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
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Data Sheet
AD9557
Rev. B | Page 39 of 92
Table 21. EEPROM Controller Instruction Set
Instruction
Value (Hex)
Instruction Type
Bytes
Required
Description
0x00 to 0x7F
Data
3
A data instruction tells the controller to transfer data to or from the device settings
part of the register map. A data instruction requires two additional bytes that,
together, indicate a starting address in the register map. Encoded in the data instruction
is the number of bytes to transfer, which is one more than the instruction value.
0x80
I/O update
1
When the controller encounters this instruction while downloading from the
EEPROM, it issues a soft I/O update.
0xA0
Calibrate
1
When the controller encounters this instruction while downloading from the
EEPROM, it initiates a system clock calibration sequence.
0xA1
Distribution sync
1
When the controller encounters this instruction while downloading from the
EEPROM, it issues a sync pulse to the output distribution synchronization.
0xB0 to 0xCF
Condition
1
B1 to CF are condition instructions and correspond to Condition 1 through
Condition 31, respectively. B0 is the null condition instruction. See the EEPROM
Conditional Processing section for details.
0xFE
Pause
1
When the controller encounters this instruction in the EEPROM storage sequence
area while uploading to the EEPROM, it holds both the register area address pointer
and the EEPROM address pointer at its last value. This allows storage of more than
one instruction sequence in the EEPROM. Note that the controller does not copy
this instruction to the EEPROM during upload.
0xFF
End
1
When the controller encounters this instruction in the EEPROM storage sequence
area while uploading to the EEPROM, it resets both the register area address pointer
and the EEPROM address pointer and then enters an idle state.
When the controller encounters this instruction while downloading from the
EEPROM, it resets the EEPROM address pointer and then enters an idle state.
EEPROM Instructions
Table 21 lists the EEPROM controller instruction set. The
controller recognizes all instruction types, whether it is in
upload or download mode, except for the pause instruction,
which is recognized only in upload mode.
The I/O update, calibrate, distribution sync, and end instruc-
tions are mostly self-explanatory. The others, however, warrant
further detail, as described in the following paragraphs.
Data instructions are those that have a value from 0x000 to
0x7FF. A data instruction tells the controller to transfer data
between the EEPROM and the register map. The controller
requires the following two parameters to carry out the data
transfer:
The number of bytes to transfer
The register map target address
The controller decodes the number of bytes to transfer directly
from the data instruction itself by adding one to the value of the
instruction. For example, the 1A data instruction has a decimal
value of 26; therefore, the controller knows to transfer 27 bytes
(one more than the value of the instruction). When the controller
encounters a data instruction, it knows to read the next two
bytes in the scratch pad because these contain the register map
target address.
Note that, in the EEPROM scratch pad, the two registers that
comprise the address portion of a data instruction have the
MSB of the address in the D7 position of the lower register
address. The bit weight increases from left to right, from the
lower register address to the higher register address. Furthermore,
the starting address always indicates the lowest numbered
register map address in the range of bytes to transfer. That is,
the controller always starts at the register map target address
and counts upward regardless of whether the serial I/O port is
operating in I2C, SPI LSB-first, or SPI MSB-first mode.
As part of the data transfer process during an EEPROM upload,
the controller calculates a 1-byte checksum and stores it as the
final byte of the data transfer. As part of the data transfer process
during an EEPROM download, however, the controller again
calculates a 1-byte checksum value but compares the newly
calculated checksum with the one that was stored during the
upload process. If an upload/download checksum pair does not
match, the controller sets the EEPROM fault status bit. If the
upload/download checksums match for all data instructions
encountered during a download sequence, the controller sets
the EEPROM complete status bit.
Condition instructions are those that have a value from B0 to
CF. The B1 to CF condition instructions represent Condition 1
to Condition 31, respectively. The B0 condition instruction is
special because it represents the null condition (see the
EEPROM Conditional Processing section).
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