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| 型号： | ADUC7033BSTZ-88-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 103/140页 |
| 文件大小： | 0K |
| 描述： | IC BATT SENSOR PREC 48LQFP |
| 标准包装： | 2,000 |
| 功能： | 电池监控器 |
| 电源电压： | 3.5 V ~ 18 V |
| 工作温度： | -40°C ~ 115°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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ADuC7033
High Voltage Configuration1 Register
Name:
Address:
Default Value:
Access:
Function:
HVCFG1
Indirectly addressed via the HVCON high voltage interface
0x00
Read/write
This 8-bit register controls the function of high voltage circuits on the ADuC7033. This register is not an MMR and
does not appear in the MMR memory map. It is accessed via the HVCON registered interface; data to be written to
this register is loaded through HVDAT and data is read back from this register using HVDAT.
Table 75. HVCFG1 Bit Designations
Bit
7
6
5
4
3
2
1
0
Description
Attenuator Enable Bit.
Cleared to 0 to disable the internal voltage attenuator and attenuator buffer.
Set to 1 to enable the internal voltage attenuator and attenuator buffer.
High Voltage Temperature Monitor. The high voltage temperature monitor is an uncalibrated temperature monitor
located on-chip close to the high voltage circuits. This monitor is completely separate to the on-chip, precision
temperature sensor (controlled via ADC1CON[7:6]) and allows user code to monitor die temperature change close to
the hottest part of the ADuC7033 die. The monitor generates a typical output voltage of 600 mV at 25°C and has a
negative temperature coefficient of typically ?2.1 mV/°C.
Set to 1 to enable the on-chip, high voltage temperature monitor. When enabled, this voltage output temperature
monitor is routed directly to the voltage channel ADC.
Cleared to 0 to disable the on-chip, high voltage temperature monitor.
Voltage Channel Short Enable Bit.
Set to 1 to enable an internal short (at the attenuator, before the ADC input buffer) on the voltage channel ADC and
allows noise be measured as a self-diagnostic test.
Cleared to 0 to disable an internal short on the voltage channel.
WU and STI Readback Enable Bit.
Cleared to 0 to disable input capability on the external WU/STI pins.
Set to 1 to enable input capability on the external WU/STI pins. In this mode, a rising or falling edge transition on the
WU/STI pins generates a high voltage interrupt. When this bit is set, the state of the WU/STI pins can be monitored via
the HVMON register (HVMON[7] and HVMON[5]).
High Voltage I/O Driver Enable Bit.
Set to 1 to re-enable any high voltage I/O pins (LIN/BSD, STI, and WU) that have been disabled as a result of a short-
circuit current event (the event must last longer than 20 μs for LIN/BSD and STI pins and 400 μs for the WU pin). This bit
must also be set to 1 to re-enable the WU and STI pins if they were disabled by a thermal event. Note that this bit must
be set to clear any pending interrupt generated by the short-circuit event (even if the event has passed) as well as re-
enabling the high voltage I/O pins.
Cleared to 0 automatically.
Enable/Disable Short-Circuit Protection (LIN/BSD and STI).
Set to 1 to enable passive short-circuit protection on the LIN pin. In this mode, a short-circuit event on the LIN/BSD pin
generates a high voltage interrupt, IRQ3 (if enabled in IRQEN[16]), and asserts the appropriate status bit in HVSTA, but
does not disable the short-circuiting pin.
Cleared to 0 to enable active short-circuit protection on the LIN/BSD pin. In this mode, during a short-circuit event, the
LIN/BSD pin generates a high voltage interrupt (IRQ3), asserts HVSTA[16], and automatically disables the short-
circuiting pin. When disabled, the I/O pin can only be re-enabled by writing to HVCFG1[3].
WU Pin Timeout (Monoflop) Counter Enable/Disable.
Set to disable the WU I/O timeout counter.
Cleared to enable a timeout counter that automatically deasserts the WU pin 1.3 seconds after user code has asserted
the WU pin via HVCFG0[4].
WU Open-Circuit Diagnostic Enable.
Set to enable an internal WU I/O diagnostic pull-up resistor to the VDD pin, thus allowing detection of an open-circuit
condition on the WU pin.
Cleared to disable an internal WU I/O diagnostic pull-up resistor.
Rev. B | Page 103 of 140
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