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参数资料
型号： ADUC7033BSTZ-88-RL
厂商： Analog Devices Inc
文件页数： 59/140页
文件大小： 0K
描述： IC BATT SENSOR PREC 48LQFP
标准包装： 2,000
功能： 电池监控器
电源电压： 3.5 V ~ 18 V
工作温度： -40°C ~ 115°C
安装类型： 表面贴装
封装/外壳： 48-LQFP
供应商设备封装： 48-LQFP（7x7）
包装： 带卷 (TR)
ADuC7033
Low Power Voltage Reference Scaling Factor
enables the ADCs to provide regular conversion results at a rate
Name:
Address:
Default
Value:
Access:
Function:
ADCREF
0xFFFF057C
Part specific, factory programmed
Read/write. This register should not be used if the
precision reference is being used in low power
mode (if ADCMDE[5] is set).
This allows user code to correct for the initial error
of the LPM reference. If the LPM voltage reference
is 1% below 1.200 V, then the value of ADCREF is
approximately 0x7EB9. If the LPM voltage reference
is 1% above 1.200 V, then the value of ADCREF is
approximately 0x8147. This register corrects the
effective value of the LPM reference at the temper-
ature the reference is measured at during Analog
Devices, Inc. production flow, which is 25°C. There
is no change to the temperature coefficient of the
LPM reference when using the ADCREF MMR.
0x8000 corresponds to no error when compared to
the normal mode reference. The magnitude of the
ADC result should be multiplied by the value in
ADCREF and divided by 0x8000 to compensate for
the actual value of the low power reference.
of between 4 Hz and 8 kHz (see the ADC Filter Register
section). Both channels are under full control of the MCU and
can be reconfigured at any time. The default ADC update rate
for all channels in this mode is 1.0 kHz.
It is worth emphasizing that I-ADC and V/T-ADC channels can
be configured to initiate periodic, normal power mode, high
accuracy, single conversion cycles before returning to ADC full
power-down mode. This flexibility is facilitated under full MCU
control via the ADCMDE MMR; it ensures that continuous peri-
odic monitoring of battery current, voltage, and temperature
settings is feasible yet ensuring the average dc current consump-
tion is minimized.
In ADC normal mode, the PLL must not be powered down.
ADC Low Power Mode
In ADC low power mode, the I-ADC is enabled in a reduced
power and reduced accuracy configuration. The ADC modu-
lator clock is driven directly from the on-chip 131 kHz low
power oscillator, which allows the ADC to be configured at
update rates as low as 1 Hz (ADCFLT). The gain of the ADC
in this mode is fixed at 128.
All of the ADC peripheral functions (result counter, digital
comparator, and accumulator) described previously in the
ADC Normal Power Mode section can still be enabled in low
power mode.
Typically, in low power mode, the I-ADC only is configured to
ADC POWER MODES OF OPERATION
The ADCs can be configured into various reduced or full power
modes of operation by configuring ADCMDE[4:3] as appropriate.
The ARM7 MCU can also be configured in low power modes of
operation (POWCON[5:3]). The core power modes are indepen-
dently controlled and are not related to the ADC power modes
described in this section. Descriptions of the ADC power
modes of operation follow.
ADC Start-Up Procedure
Prior to beginning a conversion, implement the following
procedure:
1. Configure the current ADC (ADC0) into low power mode
(ADC0CON = 0x8007; ADCMDE = 0x09).
2. Delay for 200 μs.
3. Switch the current ADC (ADC0) into idle mode
(ADCMDE = 0x03), keeping ADC0CON unchanged.
If the voltage or temperature channels are to be used,
enable them at this time.
4. Delay for 1 ms.
run at a low update rate, continuously monitoring battery
current. The MCU is in power-down mode and wakes up when
the I-ADC interrupts the MCU. This happens after the I-ADC
detects a current conversion beyond a preprogrammed threshold,
setpoint, or a set number of conversions.
It is also possible to select either the ADC precision voltage
reference or the ADC low power mode voltage reference via
ADCMDE[5].
ADC Low Power Plus Mode
In low power plus mode, the I-ADC channel is enabled in a
mode almost identical to low power mode (ADCMDE[4:3]).
However, in this mode, the I-ADC gain is fixed at 512 and the
ADC consumes an additional 200 μA (approximately) to yield
improved noise performance relative to the low power mode
setting.
Again, all of the ADC peripheral functions (result counter,
digital comparator, and accumulator) described in the ADC
Normal Power Mode section can still be enabled in low power
plus mode.
5.
Switch ADCMDE to desired mode, for example,
As in low power mode, the I-ADC only is configured to run at a
ADCMDE = 0x1.
ADC Normal Power Mode
In normal mode, the current and voltage/temperature channels
are fully enabled. The ADC modulator clock is 512 kHz and
low update rate, continuously monitoring battery current. The
MCU is in power-down mode and only wakes up when the I-ADC
interrupts the MCU. This happens after the I-ADC detects a
current conversion result beyond a preprogrammed threshold
or setpoint.
Rev. B | Page 59 of 140
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