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参数资料
| 型号： | ADUC7033BSTZ-88-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/140页 |
| 文件大小： | 0K |
| 描述： | IC BATT SENSOR PREC 48LQFP |
| 标准包装： | 2,000 |
| 功能： | 电池监控器 |
| 电源电压： | 3.5 V ~ 18 V |
| 工作温度： | -40°C ~ 115°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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ADuC7033
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Normal interrupt (IRQ). This is provided to service
general-purpose interrupt handling of internal and
external events.
Fast interrupt (FIQ). This is provided to service data
transfer or a communication channel with low latency. FIQ
has priority over IRQ.
Memory abort (prefetch and data).
Attempted execution of an undefined instruction.
Software interrupt (SWI) instruction that can be used to
in Figure 11. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly
from ARM Ltd.
make a call to an operating system.
Typically, the programmer defines interrupts as IRQ, but for
higher priority interrupts, the programmer can define interrupts
as the FIQ type.
The priority of these exceptions and vector addresses are listed
R0
R1
R2
R3
R4
R5
R6
USABLE IN USER MODE
SYSTEM MODES ONLY
Table 9. Exception Priorities and Vector Addresses
Priority Exception Address
1 Hardware Reset 0x00
2 Memory Abort (Data) 0x10
3 FIQ 0x1C
R7
R8
R9
R10
R11
R12
R13
R14
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_SVC
R14_SVC
R13_ABT
R14_ABT
R13_IRQ
R14_IRQ
R13_UND
R14_UND
4
IRQ
0x18
R15 (PC)
5
6
Memory Abort (Prefetch)
Software Interrupt 1
0x0C
0x08
CPSR
SPSR_FIQ
SPSR_SVC
SPSR_ABT
SPSR_IRQ
SPSR_UND
A software interrupt and an undefined instruction exception have the same
1
6 Undefined Instruction 1 0x04
priority and are mutually exclusive.
USER MODE
FIQ SVC ABORT IRQ
MODE MODE MODE MODE
Figure 11. Register Organization
UNDEFINED
MODE
The list of exceptions in Table 9 are located from 0x00 to 0x1C,
with a reserved location at 0x14. This location must be written
with either 0x27011970 or the checksum of Page Zero, excluding
Location 0x14. If this is not done, user code does not execute
and LIN download mode is entered.
ARM Registers
The ARM7TDMI has 16 standard registers. R0 to R12 are for
data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched (if the branch
and link command was used) or the command during which an
exception occurred.
The stack pointer contains the current location of the stack.
Generally, on an ARM7TDMI, the stack starts at the top of the
available RAM area and descends using the area as required. A
separate stack is defined for each of the exceptions. The size of
each stack is user configurable and is dependent on the target
application. On the ADuC7033, the stack begins at 0x00040FFC
and descends. When programming using high level languages,
such as C, it is necessary to ensure that the stack does not overflow.
This is dependent on the performance of the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
Interrupt Latency
The worst-case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest instruc-
tion is an LDM) that loads all the registers including the PC, plus
the time for the data abort entry, plus the time for FIQ entry. At
the end of this time, the ARM7TDMI is executing the instruc-
tion at 0x1C (FIQ interrupt vector address). The maximum total
time is 50 processor cycles, or just over 2.44 μs in a system using
a continuous 20.48 MHz processor clock. The maximum IRQ
latency calculation is similar, but must allow for the fact that FIQ
has higher priority and can delay entry into the IRQ handling
routine for an arbitrary length of time. This time can be reduced
to 42 cycles if the LDM command is not used; some compilers
have an option to compile without using this command. Another
option is to run the part in Thumb mode where this is reduced
to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if
required, for example, when executing interrupt service
routines.
stack pointer (R13) and the link register (R14) as represented
Rev. B | Page 22 of 140
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADUC7033BSTZ-8L | 制造商:Analog Devices 功能描述:INTEGRATED PRECISION BATTERY SENSOR 48LQFP - Trays 制造商:Rochester Electronics LLC 功能描述: |
| ADUC7033BSTZ-8L-RL | 制造商:Analog Devices 功能描述:INTEGRATED PRECISION BATTERY SENSOR 48LQFP - Tape and Reel |
| ADUC7033BSTZ8VTCRL | 制造商:Analog Devices 功能描述: |
| ADUC7034 | 制造商:AD 制造商全称:Analog Devices 功能描述:Integrated Precision Battery Sensor for Automotive |
| ADUC7034BCPZ | 功能描述:IC MCU FLASH 32K ANLG IO 48LFCSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 标准包装:38 系列:Encore!® XP® 核心处理器:eZ8 芯体尺寸:8-位 速度:5MHz 连通性:IrDA，UART/USART 外围设备:欠压检测/复位，LED，POR，PWM，WDT 输入/输出数:16 程序存储器容量:4KB（4K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:1K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 3.6 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 105°C 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 包装:管件 其它名称:269-4116Z8F0413SH005EG-ND |
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