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| 型号： | ADUC7033BSTZ-88-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 69/140页 |
| 文件大小： | 0K |
| 描述： | IC BATT SENSOR PREC 48LQFP |
| 标准包装： | 2,000 |
| 功能： | 电池监控器 |
| 电源电压： | 3.5 V ~ 18 V |
| 工作温度： | -40°C ~ 115°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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ADuC7033
Table 46. POWCON MMR Bit Designations
Bit
31 to 8
7
6
5
4
3
2 to 0
Description
Reserved.
Precision 131 kHz Input Enable.
Cleared by the user to power-down the precision 131 kHz input enable.
Set by the user to enable the precision 131 kHz input enable. The precision 131 kHz oscillator must also be enabled
using HVCFG0[6]. Setting this bit increases current consumption by approximately 50 μA and should be disabled when
not in use.
XTAL Power-Down.
Cleared by the user to power down the external crystal circuitry.
Set by the user to enable the external crystal circuitry.
PLL Power-Down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock
source remain in normal power mode.
Cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are enabled: Bit
3, Bit 4, and Bit 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake-up event.
Peripherals Power-Down. The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE memory and
GPIO interfaces, and SPI and UART serial ports.
Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled: Bit 3 and Bit 4
must be cleared simultaneously. LIN can still respond to wake-up events even if this bit is cleared. The wake-up timer
(Timer2) can remain active if driven from a low power oscillator even if this bit is cleared.
Set by default, and/or by hardware, on a wake-up event.
Core Power-Down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is
written to POWCON.
Cleared to power down the ARM core.
Set by default, and set by hardware on a wake-up event.
CD Core Clock Divider Bits.
000 = 20.48 MHz, 48.83 ns.
001 = 10.24 MHz, 97.66 ns.
010 = 5.12 MHz, 195.31 ns.
011 = 2.56 MHz, 390.63 ns.
100 = 1.28 MHz, 781.25 ns.
101 = 640 kHz, 1.56 μs.
110 = 320 kHz, 3.125 μs.
111 = 160 kHz, 6.25 μs.
LOW POWER CLOCK CALIBRATION
The low power 131 kHz oscillator can be calibrated using either
the precision 131 kHz oscillator or an external 32.768 kHz
watch crystal. Two dedicated calibration counters and an
oscillator trim register are used to implement this feature.
One counter, nine bits wide, is clocked by either the precision
oscillator or the external watch crystal. The second counter,
10 bits wide, is clocked by the low power oscillator, either
directly at 131 kHz, or through a divide-by-4 block generating
32.768 kHz. The source for each calibration counter should be
of the same frequency. The trim register (OSC0TRM) is an 8-bit
wide register, the lower four bits of which are user-accessible
trim bits. Increasing the value in OSC0TRM decreases the
The clock calibration mode is configured and controlled by the
following MMRs:
OSC0CON—control bits for calibration.
OSC0STA—calibration status register.
OSC0VAL0—9-bit counter, Counter 0.
OSC0VAL1—10-bit counter, Counter 1.
OSC0TRM—oscillator trim register.
An example calibration routine is shown in Figure 30. User
code configures and enables the calibration sequence using
OSC0CON. When the precision oscillator calibration counter
(OSC0VAL0) reaches 0x1FF, both counters are disabled.
frequency of the low power oscillator; decreasing the value
increases the frequency. Based on a nominal frequency of
131 kHz, the typical trim range is between 127 kHz to 135 kHz.
Rev. B | Page 69 of 140
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