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参数资料
| 型号： | ADUC7033BSTZ-88-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 132/140页 |
| 文件大小： | 0K |
| 描述： | IC BATT SENSOR PREC 48LQFP |
| 标准包装： | 2,000 |
| 功能： | 电池监控器 |
| 电源电压： | 3.5 V ~ 18 V |
| 工作温度： | -40°C ~ 115°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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ADuC7033
BSD DATA RECEPTION
BUS PULLED LOW
BY MASTER
t SYNC
t 0
BUS RELEASED BY
SLAVE AFTER t 0
BUS HELD LOW
BY SLAVE
RELEASED BY
MASTER
To receive data, the LIN/BSD peripheral must first be con-
figured in BSD mode where LHSCON[6] = 1. In this mode,
LHSCON0[8] should be set to ensure the LHS break timer
Figure 55. BSD Slave Transmitting Zero
Typical BSD Program Flow
Because BSD is a PWM communications protocol controlled by
software, it is necessary for the user to construct the required
data from each bit. For example, in constructing the slave
address, the slave node receives the three bits and the user
constructs the relevant address.
section) generates an interrupt on the rising edge of the BSD bus.
The LHS break timer is cleared and starts counting on the
falling edge of the BSD bus and is subsequently stopped and
generates an interrupt on the rising edge of the BSD bus. Given
that the LHS break timer is clocked by the low power (131 kHz)
oscillator, the value in LHSVAL1 can be interpreted by user code
to determine if the received data bit is a BSD sync pulse, 0, or 1.
When the master initiates BSD, data is transmitted and received
by the slave node. A flow diagram showing this process is
INITIALIZE BSD
HARDWARE/
SOFTWARE
1 LHSVAL1 CLEARED
AND STARTS COUNTING
ON THIS EDGE
2 LHSVAL1 STOPPED
AND GENERATES
INTERRUPT ON THIS EDGE
BSD ‘1’ PERIOD
BSD ‘0’ PERIOD
Figure 57. Master Transmit, Slave Read
RECEIVE
SYNCHRONIZATION
PULSES
RECEIVE
DIRECTION
BIT
RECEIVE
SLAVE
ADDRESS
RECEIVE
REGISTER
ADDRESS
RECEIVE FIRST
PARITY BIT
BSD DATA TRANSMISSION
User code forces a GPIO signal (GPIO_12) low for a specified
time to transmit data in BSD mode. In addition, user code uses
the sync timer (LHSVAL0), LHS sync capture register (LHSCAP),
and the LHS sync compare register (LHSCMP) to time how
long the BSD bus should be held low for 0 or 1 bit transmissions.
As described previously, even when the slave is transmitting, the
master always starts the bit transmission period by pulling the
BSD bus low. If BSD mode is selected (LHSCON0[6] = 1), the
LIN sync timer value is captured in LHSCAP on every falling
edge of the BSD bus. The LIN sync timer runs continuously in
BSD mode.
User code can then immediately force GPIO_12 low and reads
the captured timer value from LHSCAP. A calculation of how
many (5 MHz) clock periods should elapse before the GPIO_12
should be driven high for a 0 or 1 pulse width can be made.
RECEIVE DATA
FROM MASTER
RECEIVE SECOND
PARITY BIT
TRANSMIT
ACK/NACK
TRANSMIT DATA
TO MASTER
TRANSMIT SECOND
PARITY BIT
This number is added to the LHSCAP value and written into
the LHSCMP register. If LHSCON0[5] is set, the sync timer,
which continues to count (being clocked by a 5 MHz clock),
eventually equals the LHSCMP value and generates an LHS
compare interrupt (LHSSTA[3]).
The response to this interrupt should be to force the GPIO_12
signal (and, therefore, the BSD bus) high. The software control
of the GPIO_12 signal along with the correct use of the LIN
synchronization timers ensures that valid 0 and 1 pulse widths
Figure 56. BSD Slave Node State Machine
Again, care needs to be taken when switching from BSD write
mode to BSD read mode, as described in LHSCON0[8].
Rev. B | Page 132 of 140
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| ADUC7033BSTZ-8L | 制造商:Analog Devices 功能描述:INTEGRATED PRECISION BATTERY SENSOR 48LQFP - Trays 制造商:Rochester Electronics LLC 功能描述: |
| ADUC7033BSTZ-8L-RL | 制造商:Analog Devices 功能描述:INTEGRATED PRECISION BATTERY SENSOR 48LQFP - Tape and Reel |
| ADUC7033BSTZ8VTCRL | 制造商:Analog Devices 功能描述: |
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