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| 型号： | DK-DEV-3CLS200N |
| 厂商： | Altera |
| 文件页数： | 10/34页 |
| 文件大小： | 0K |
| 描述： | KIT DEV CYCLONE III LS EP3CLS200 |
| 产品培训模块： | Cyclone® III FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3CLS200 |
| 所含物品： | 板 |
| 产品目录页面： | 606 (CN2011-ZH PDF) |
| 相关产品： | 544-2564-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2563-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2562-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2561-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2560-ND - IC CYCLONE III FPGA 5K 256 UBGA 544-2559-ND - IC CYCLONE III FPGA 5K 164 MBGA 544-2558-ND - IC CYCLONE III FPGA 5K 256 FBGA 544-2557-ND - IC CYCLONE III FPGA 5K 144 EQFP 544-2556-ND - IC CYCLONE III FPGA 55K 484 UBGA 544-2554-ND - IC CYCLONE III FPGA 55K 780 FBGA 更多... |
| 其它名称： | 544-2601 |
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1–10
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Schmitt Trigger Input
Cyclone III devices support Schmitt trigger input on TDI , TMS , TCK , nSTATUS , nCONFIG ,
nCE , CONF_DONE , and DCLK pins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate.
trigger inputs in Cyclone III devices.
Table 1–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices
Symbol
V SCHMITT
Parameter
Hysteresis for Schmitt trigger
input
Conditions
V CCIO = 3.3 V
V CCIO = 2.5 V
V CCIO = 1.8 V
V CCIO = 1.5 V
Minimum
200
200
140
110
Typical
—
—
—
—
Maximum
—
—
—
—
Unit
mV
mV
mV
mV
I/O Standard Specifications
The following tables list input voltage sensitivities (V IH and V IL ), output voltage (V OH
and V OL ), and current drive characteristics (I OH and I OL ) for various I/O standards
supported by Cyclone III devices. Table 1–13 through Table 1–18 provide the I/O
standard specifications for Cyclone III devices.
Table 1–13. Cyclone III Devices Single-Ended I/O Standard Specifications
I/O Standard
Min
V CCIO (V)
Typ
Max
V IL (V)
Min Max
Min
V IH (V)
Max
V OL (V)
Max
V OH (V)
Min
I OL
(mA)
I OH
(mA)
3.3-V LVTTL
3.135
3.3
3.465
—
0.8
1.7
3.6
0.45
2.4
4
–4
3.3-V LVCMOS
3.135
3.3
3.465
—
0.8
1.7
3.6
0.2
V CCIO – 0.2
2
–2
3.0-V LVTTL
2.85
3.0
3.15
–0.3
0.8
1.7
V CCIO + 0.3
0.45
2.4
4
–4
3.0-V LVCMOS
2.85
3.0
3.15
–0.3
0.8
1.7
V CCIO + 0.3
0.2
V CCIO – 0.2
0.1
–0.1
2.5-V LVTTL and
LVCMOS (3)
1.8-V LVTTL and
LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
2.375
1.71
1.425
1.14
2.5
1.8
1.5
1.2
2.625
1.89
1.575
1.26
–0.3
–0.3
–0.3
–0.3
0.7
0.35 *
V CCIO
0.35 *
V CCIO
0.35 *
V CCIO
1.7
0.65 *
V CCIO
0.65 *
V CCIO
0.65 *
V CCIO
3.6
2.25
V CCIO + 0.3
V CCIO + 0.3
0.4
0.45
0.25 *
V CCIO
0.25 *
V CCIO
2.0
V CCIO –
0.45
0.75 *
V CCIO
0.75 *
V CCIO
1
2
2
2
–1
–2
–2
–2
3.0-V PCI
3.0-V PCI-X
2.85
2.85
3.0
3.0
3.15
3.15
—
—
0.3 *
V CCIO
0.35*
V CCIO
0.5 *
V CCIO
0.5 *
V CCIO
V CCIO + 0.3 0.1 * V CCIO
V CCIO + 0.3 0.1 * V CCIO
0.9 * V CCIO
0.9 * V CCIO
1.5
1.5
–0.5
–0.5
(1) For voltage referenced receiver input waveform and explanation of terms used in Table 1–13 , refer to “Single-ended Voltage referenced I/O Standard”
(2) AC load CL = 10 pF.
(3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III
July 2012 Altera Corporation
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