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参数资料
型号： DK-DEV-3CLS200N
厂商： Altera
文件页数： 16/34页
文件大小： 0K
描述： KIT DEV CYCLONE III LS EP3CLS200
产品培训模块： Cyclone® III FPGA
Three Reasons to Use FPGA's in Industrial Designs
标准包装： 1
系列： Cyclone® III
类型： FPGA
适用于相关产品： EP3CLS200
所含物品： 板
产品目录页面： 606 (CN2011-ZH PDF)
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544-2560-ND - IC CYCLONE III FPGA 5K 256 UBGA
544-2559-ND - IC CYCLONE III FPGA 5K 164 MBGA
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其它名称： 544-2601
1–16
Table 1–20. Cyclone III Devices PLL Specifications (1)
(Part 2 of 2)
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
f SCANCLK
Symbol
scanclk frequency
Parameter
Min
—
Typ
—
Max
100
Unit
MHz
Notes to Table 1–20 :
(1) V CCD_PLL should always be connected to V CCINT through decoupling capacitor and ferrite bead.
(2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(3) The V CO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the V CO post-scale
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f VCO specification.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
(5) Peak-to-peak jitter with a probability level of 10 –12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic
jitter of the PLL, when an input jitter of 30 ps is applied.
(6) With 100 MHz scanclk frequency.
Embedded Multiplier Specifications
Table 1–21 describes the embedded multiplier specifications for Cyclone III devices.
Table 1–21. Cyclone III Devices Embedded Multiplier Specifications
Mode
Resources Used
Performance
Unit
Number of Multipliers
C6
C7, I7, A7
C8
9 × 9-bit
multiplier
18 × 18-bit
multiplier
1
1
340
287
300
250
260
200
MHz
MHz
Memory Block Specifications
Table 1–22 describes the M9K memory block specifications for Cyclone III devices.
Table 1–22. Cyclone III Devices Memory Block Performance Specifications
Resources Used
Performance
Memory
M9K Block
Mode
FIFO 256 × 36
Single-port 256 × 36
Simple dual-port 256 × 36 CLK
True dual port 512 × 18 single CLK
LEs
47
0
0
0
M9K
Memory
1
1
1
1
C6
315
315
315
315
C7, I7, A7
274
274
274
274
C8
238
238
238
238
Unit
MHz
MHz
MHz
MHz
Configuration and JTAG Specifications
Table 1–23 lists the configuration mode specifications for Cyclone III devices.
Table 1–23. Cyclone III Devices Configuration Mode Specifications
Programming Mode
Passive Serial (PS)
DCLK F max
133
Unit
MHz
Fast Passive Parallel (FPP)
(1)
100
MHz
Note to Table 1–23 :
(1) EP3C40 and smaller density members support 133 MHz.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
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