参数资料
型号: DK-DEV-3CLS200N
厂商: Altera
文件页数: 4/34页
文件大小: 0K
描述: KIT DEV CYCLONE III LS EP3CLS200
产品培训模块: Cyclone® III FPGA
Three Reasons to Use FPGA's in Industrial Designs
标准包装: 1
系列: Cyclone® III
类型: FPGA
适用于相关产品: EP3CLS200
所含物品:
产品目录页面: 606 (CN2011-ZH PDF)
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其它名称: 544-2601
1–4
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Cyclone III devices. The steady-state voltage and current values expected from
Cyclone III devices are provided in Table 1–3 . All supplies must be strictly monotonic
without plateaus.
Table 1–3. Cyclone III Devices Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V CCINT
Supply voltage for internal logic
Supply voltage for output buffers, 3.3-V
operation
Supply voltage for output buffers, 3.0-V
operation
1.15
3.135
2.85
1.2
3.3
3
1.25
3.465
3.15
V
V
V
V CCIO
V CCA
Supply voltage for output buffers, 2.5-V
operation
Supply voltage for output buffers, 1.8-V
operation
Supply voltage for output buffers, 1.5-V
operation
Supply voltage for output buffers, 1.2-V
operation
Supply (analog) voltage for PLL
regulator
2.375
1.71
1.425
1.14
2.375
2.5
1.8
1.5
1.2
2.5
2.625
1.89
1.575
1.26
2.625
V
V
V
V
V
V CCD_PLL
V I
V O
Supply (digital) voltage for PLL
Input voltage
Output voltage
1.15
–0.5
0
1.2
1.25
3.6
V CCIO
V
V
V
For commercial use
0
85
°C
T J
t RAMP
I Diode
Operating junction temperature
Power supply ramp time
Magnitude of DC current across
PCI-clamp diode when enabled
For industrial use
For extended temperature
For automotive use
Standard power-on reset
(POR) (5)
Fast POR
–40
–40
–40
50 μs
50 μs
100
125
125
50 ms
3 ms
10
°C
°C
°C
mA
Notes to Table 1–3 :
(1) V CCIO for all I/O banks must be powered up during device operation. All V CCA pins must be powered to 2.5 V (even when PLLs are not used), and
must be powered up and powered down at the same time.
(2) V CCD_PLL must always be connected to V CCINT through a decoupling capacitor and ferrite bead.
(3) The V CC must rise monotonically.
(4) All input buffers are powered by the V CCIO supply.
(5) POR time for Standard POR ranges between 50–200 ms. Each individual power supply should reach the recommended operating range within
50 ms.
(6) POR time for Fast POR ranges between 3–9 ms. Each individual power supply should reach the recommended operating range within 3 ms.
July 2012 Altera Corporation
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