参数资料
型号: DK-DEV-3CLS200N
厂商: Altera
文件页数: 6/34页
文件大小: 0K
描述: KIT DEV CYCLONE III LS EP3CLS200
产品培训模块: Cyclone® III FPGA
Three Reasons to Use FPGA's in Industrial Designs
标准包装: 1
系列: Cyclone® III
类型: FPGA
适用于相关产品: EP3CLS200
所含物品:
产品目录页面: 606 (CN2011-ZH PDF)
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其它名称: 544-2601
1–6
Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Table 1–5. Cyclone III Devices Bus Hold Parameter
(Part 2 of 2)
(1)
V CCIO (V)
Parameter
Condition
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold
low,
overdrive
0 V < V IN < V CCIO
125
175
200
300
500
500
? A
current
Bus-hold
high,
overdrive
0 V < V IN < V CCIO
–125
–175
–200
–300
–500
–500
? A
current
Bus-hold trip
point
0.3
0.9
0.375 1.125
0.68
1.07
0.7
1.7
0.8
2
0.8
2
V
Note to Table 1–5 :
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
OCT Specifications
Table 1–6 lists the variation of OCT without calibration across process, temperature,
and voltage.
Table 1–6. Cyclone III Devices Series OCT without Calibration Specifications
Resistance Tolerance
Description
V CCIO (V)
Commercial
Industrial and Automotive
Unit
Max
Max
3.0
2.5
±30
±30
±40
±40
%
%
Series OCT without
calibration
1.8
1.5
1.2
+40
+50
+50
±50
±50
±50
%
%
%
OCT calibration is automatically performed at device power-up for OCT enabled
I/Os.
Table 1–7 lists the OCT calibration accuracy at device power-up.
Table 1–7. Cyclone III Devices Series OCT with Calibration at Device Power-Up Specifications
Calibration Accuracy
Description
Series OCT with
calibration at device
power-up
V CCIO (V)
3.0
2.5
1.8
1.5
1.2
Commercial Max
±10
±10
±10
±10
±10
Industrial and Automotive
Max
±10
±10
±10
±10
±10
Unit
%
%
%
%
%
July 2012 Altera Corporation
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