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| 型号： | DK-DEV-3CLS200N |
| 厂商： | Altera |
| 文件页数： | 29/34页 |
| 文件大小： | 0K |
| 描述： | KIT DEV CYCLONE III LS EP3CLS200 |
| 产品培训模块： | Cyclone® III FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3CLS200 |
| 所含物品： | 板 |
| 产品目录页面： | 606 (CN2011-ZH PDF) |
| 相关产品： | 544-2564-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2563-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2562-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2561-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2560-ND - IC CYCLONE III FPGA 5K 256 UBGA 544-2559-ND - IC CYCLONE III FPGA 5K 164 MBGA 544-2558-ND - IC CYCLONE III FPGA 5K 256 FBGA 544-2557-ND - IC CYCLONE III FPGA 5K 144 EQFP 544-2556-ND - IC CYCLONE III FPGA 55K 484 UBGA 544-2554-ND - IC CYCLONE III FPGA 55K 780 FBGA 更多... |
| 其它名称： | 544-2601 |
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Chapter 1: Cyclone III Device Datasheet
Glossary
Table 1–39. Glossary (Part 3 of 5)
1–29
Letter
Term
V OH
Definitions
V IH(DC)
V IH (AC )
V CCIO
Single-ended
Voltage
V REF
V IL(DC)
V IL(AC )
S
referenced I/O
Standard
V OL
V SS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing .
SW (Sampling
Window)
t C
TCCS (Channel-
to-channel-skew)
tcin
t CO
tcout
t DUTY
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
High-speed receiver/transmitter input and output clock period.
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,
including t CO variation and clock skew. The clock is included in the TCCS measurement.
Delay from clock pad to I/O input register.
Delay from clock pad to I/O output.
Delay from clock pad to I/O output register.
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
T
July 2012
t FALL
t H
Timing Unit
Interval (TUI)
t INJITTER
t OUTJITTER_DEDCLK
t OUTJITTER_IO
tpllcin
tpllcout
Altera Corporation
Signal High-to-low transition time (80–20%).
Input register hold time.
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t C /w).
Period jitter on PLL clock input.
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
Delay from PLL inclk pad to I/O input register.
Delay from PLL inclk pad to I/O output register.
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