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| 型号： | DK-DEV-3CLS200N |
| 厂商： | Altera |
| 文件页数： | 15/34页 |
| 文件大小： | 0K |
| 描述： | KIT DEV CYCLONE III LS EP3CLS200 |
| 产品培训模块： | Cyclone® III FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3CLS200 |
| 所含物品： | 板 |
| 产品目录页面： | 606 (CN2011-ZH PDF) |
| 相关产品： | 544-2564-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2563-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2562-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2561-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2560-ND - IC CYCLONE III FPGA 5K 256 UBGA 544-2559-ND - IC CYCLONE III FPGA 5K 164 MBGA 544-2558-ND - IC CYCLONE III FPGA 5K 256 FBGA 544-2557-ND - IC CYCLONE III FPGA 5K 144 EQFP 544-2556-ND - IC CYCLONE III FPGA 55K 484 UBGA 544-2554-ND - IC CYCLONE III FPGA 55K 780 FBGA 更多... |
| 其它名称： | 544-2601 |
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Chapter 1: Cyclone III Device Datasheet
1–15
Switching Characteristics
PLL Specifications
the commercial junction temperature range (0°C to 85°C), the industrial junction
temperature range (–40°C to 100°C), and the automotive junction temperature range
(–40°Cto 125°C). For more information about PLL block, refer to “PLL Block” in
Table 1–20. Cyclone III Devices PLL Specifications (1)
(Part 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
f IN
Input clock frequency
5
—
472.5
MHz
f INPFD
PFD input frequency
5
—
325
MHz
f VCO
PLL internal VCO operating range
600
—
1300
MHz
f INDUTY
Input clock duty cycle
40
—
60
%
t INJITTER_CCJ
Input clock cycle-to-cycle jitter for F INPFD ? 100 MHz
Input clock cycle-to-cycle jitter for F INPFD < 100 MHz
—
—
—
—
0.15
±750
UI
ps
f OUT_EXT (external clock output)
f OUT (to global clock)
t OUTDUTY
t LOCK
PLL output frequency
PLL output frequency (–6 speed grade)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
Duty cycle for external clock output (when set to 50%)
Time required to lock from end of device configuration
—
—
—
—
45
—
—
—
—
—
50
—
472.5
472.5
450
402.5
55
1
MHz
MHz
MHz
MHz
%
ms
Time required to lock dynamically (after switchover,
t DLOCK
reconfiguring any non-post-scale counters/delays or
—
—
1
ms
areset is deasserted)
t OUTJITTER_PERIOD_DEDCLK
Dedicated clock output period jitter
F OUT ? 100 MHz
F OUT < 100 MHz
—
—
—
—
300
30
ps
mUI
t OUTJITTER_CCJ_DEDCLK
Dedicated clock output cycle-to-cycle jitter
F OUT ? 100 MHz
F OUT < 100 MHz
—
—
—
—
300
30
ps
mUI
t OUTJITTER_PERIOD_IO
Regular I/O period jitter
F OUT ? 100 MHz
F OUT < 100 MHz
—
—
—
—
650
75
ps
mUI
t OUTJITTER_CCJ_IO
t PLL_PSERR
t ARESET
Regular I/O cycle-to-cycle jitter
F OUT ? 100 MHz
F OUT < 100 MHz
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
—
—
—
10
—
—
—
—
650
75
±50
—
ps
mUI
ps
ns
t CONFIGPLL
Time required to reconfigure scan chains for PLLs
—
3.5
—
SCANCLK
cycles
July 2012
Altera Corporation
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