参数资料
型号: DK-DEV-3CLS200N
厂商: Altera
文件页数: 18/34页
文件大小: 0K
描述: KIT DEV CYCLONE III LS EP3CLS200
产品培训模块: Cyclone® III FPGA
Three Reasons to Use FPGA's in Industrial Designs
标准包装: 1
系列: Cyclone® III
类型: FPGA
适用于相关产品: EP3CLS200
所含物品: 板
产品目录页面: 606 (CN2011-ZH PDF)
相关产品: 544-2564-ND - IC CYCLONE III FPGA 80K 484 UBGA
544-2563-ND - IC CYCLONE III FPGA 80K 484 UBGA
544-2562-ND - IC CYCLONE III FPGA 80K 484 FBGA
544-2561-ND - IC CYCLONE III FPGA 80K 484 FBGA
544-2560-ND - IC CYCLONE III FPGA 5K 256 UBGA
544-2559-ND - IC CYCLONE III FPGA 5K 164 MBGA
544-2558-ND - IC CYCLONE III FPGA 5K 256 FBGA
544-2557-ND - IC CYCLONE III FPGA 5K 144 EQFP
544-2556-ND - IC CYCLONE III FPGA 55K 484 UBGA
544-2554-ND - IC CYCLONE III FPGA 55K 780 FBGA
更多...
其它名称: 544-2601
1–18
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
High-Speed I/O Specifications
Table 1–26 through Table 1–31 list the high-speed I/O timing for Cyclone III devices.
For definitions of high-speed timing specifications, refer to “Glossary” on page 1–27 .
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
×10
×8
5
5
—
—
180
180
5
5
—
—
155.5
155.5
5
5
—
—
155.5
155.5
MHz
MHz
f HSCLK
(input clock
frequency)
Device operation in
Mbps
t DUTY
TCCS
Output jitter
(peak to peak)
t RISE
t FALL
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
—
20 – 80%, C LOAD =
5 pF
20 – 80%, C LOAD =
5 pF
5
5
5
5
100
80
70
40
20
10
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
500
180
180
180
360
360
360
360
360
360
360
55
200
500
—
—
5
5
5
5
100
80
70
40
20
10
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
500
155.5
155.5
155.5
311
311
311
311
311
311
311
55
200
500
—
—
5
5
5
5
100
80
70
40
20
10
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
500
500
155.5
155.5
155.5
311
311
311
311
311
311
311
55
200
550
—
—
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
ps
ps
ps
ps
t LOCK
—
—
—
1
—
—
1
—
—
1
ms
Notes to Table 1–26 :
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.
(2) True RSDS transmitter is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS transmitter is supported at the output
pin of all I/O banks.
(3) t LOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (1) (Part 1 of 2)
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
×10
×8
5
5
—
—
85
85
5
5
—
—
85
85
5
5
—
—
85
85
MHz
MHz
f HSCLK (input
clock
frequency)
×7
×4
×2
×1
5
5
5
5
—
—
—
—
85
85
85
170
5
5
5
5
—
—
—
—
85
85
85
170
5
5
5
5
—
—
—
—
85
85
85
170
MHz
MHz
MHz
MHz
July 2012 Altera Corporation
相关PDF资料
PDF描述
FPF2000 IC SW LOAD FULL FUNC 50MA SC70-5
DC1813A-A BOARD SAR ADC LTC2370-16
EEM25DRYF CONN EDGECARD 50POS DIP .156 SLD
VE-B5V-EY CONVERTER MOD DC/DC 5.8V 50W
ESM10DREN CONN EDGECARD 20POS .156 EYELET
相关代理商/技术参数
参数描述
DK-DEV-3SL150N 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP3SL150F152 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
DK-DEV-3SL150N/ES 制造商:Altera Corporation 功能描述:KIT DEVELOPMENT STRATIX II ES
DK-DEV-4CGX150N 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP4CGX150 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
DK-DEV-4CGX150N 制造商:Altera Corporation 功能描述:KIT STARTER CYCLONE IV GX ((NS
DK-DEV-4S100G5N 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP4S100G5F RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: