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| 型号： | DK-DEV-3CLS200N |
| 厂商： | Altera |
| 文件页数： | 22/34页 |
| 文件大小： | 0K |
| 描述： | KIT DEV CYCLONE III LS EP3CLS200 |
| 产品培训模块： | Cyclone® III FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3CLS200 |
| 所含物品： | 板 |
| 产品目录页面： | 606 (CN2011-ZH PDF) |
| 相关产品： | 544-2564-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2563-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2562-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2561-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2560-ND - IC CYCLONE III FPGA 5K 256 UBGA 544-2559-ND - IC CYCLONE III FPGA 5K 164 MBGA 544-2558-ND - IC CYCLONE III FPGA 5K 256 FBGA 544-2557-ND - IC CYCLONE III FPGA 5K 144 EQFP 544-2556-ND - IC CYCLONE III FPGA 55K 484 UBGA 544-2554-ND - IC CYCLONE III FPGA 55K 780 FBGA 更多... |
| 其它名称： | 544-2601 |
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1–22
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 2 of 2)
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
Max
Min
Max
Min
Max
Output jitter
(peak to peak)
—
—
500
—
500
—
550
ps
t LOCK
—
—
1
—
1
—
1
ms
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.
(2) t LOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
Max
Min
Max
Min
Max
×10
×8
5
5
437.5
437.5
5
5
370
370
5
5
320
320
MHz
MHz
f HSCLK (input
clock frequency)
HSIODR
SW
Input jitter
tolerance
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
5
5
5
5
100
80
70
40
20
10
—
—
437.5
437.5
437.5
437.5
875
875
875
875
875
437.5
400
500
5
5
5
5
100
80
70
40
20
10
—
—
370
370
370
402.5
740
740
740
740
740
402.5
400
500
5
5
5
5
100
80
70
40
20
10
—
—
320
320
320
402.5
640
640
640
640
640
402.5
400
550
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
ps
t LOCK
—
—
1
—
1
—
1
ms
(1) LVDS receiver is supported at all banks.
(2) t LOCK is the time required for the PLL to lock from the end of device configuration.
External Memory Interface Specifications
Cyclone III devices support external memory interfaces up to 200 MHz. The external
memory interfaces for Cyclone III devices are auto-calibrating and easy to implement.
f For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
July 2012 Altera Corporation
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