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| 型号： | DK-DEV-3CLS200N |
| 厂商： | Altera |
| 文件页数： | 33/34页 |
| 文件大小： | 0K |
| 描述： | KIT DEV CYCLONE III LS EP3CLS200 |
| 产品培训模块： | Cyclone® III FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3CLS200 |
| 所含物品： | 板 |
| 产品目录页面： | 606 (CN2011-ZH PDF) |
| 相关产品： | 544-2564-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2563-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2562-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2561-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2560-ND - IC CYCLONE III FPGA 5K 256 UBGA 544-2559-ND - IC CYCLONE III FPGA 5K 164 MBGA 544-2558-ND - IC CYCLONE III FPGA 5K 256 FBGA 544-2557-ND - IC CYCLONE III FPGA 5K 144 EQFP 544-2556-ND - IC CYCLONE III FPGA 55K 484 UBGA 544-2554-ND - IC CYCLONE III FPGA 55K 780 FBGA 更多... |
| 其它名称： | 544-2601 |
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Chapter 1: Cyclone III Device Datasheet
Document Revision History
Table 1–40. Document Revision History (Part 2 of 3)
1–33
Date
Version
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Changes
Updated “Operating Conditions” section and included information on automotive device.
Updated Table 1–3, Table 1–6, and Table 1–7, and added automotive information.
Under “Pin Capacitance” section, updated Table 1–9 and Table 1–10.
Added new “Schmitt Trigger Input” section with Table 1–12.
Under “I/O Standard Specifications” section, updated Table 1–13, 1–12 and 1–12.
May 2008
2.0
■
Under “Switching Characteristics” section, updated Table 1–19, 1–15, 1–16, 1–16, 1–17,
1–18, 1–19, 1–20, 1–21, 1–21, 1–23, 1–23, 1–23, 1–24, and 1–25.
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Updated Figure 1–5 and 1–29.
Deleted previous Table 1-35 “DDIO Outputs Half-Period Jitter”.
Under “I/O Timing” section, updated Table 1–38, 1–29, 1–32, 1–33, 1–26, and 1–26.
Under “Typical Design Performance” section updated Table 1–46 through 1–145.
Under “Core Performance Specifications”, updated Tables 1-18 and 1-19.
Under “Preliminary, Correlated, and Final Timing”, updated Table 1-37.
December 2007
1.5
■
Under “Typical Design Performance”, updated Tables 1-45, 1-46, 1-51, 1-52, 1-57, 1-58,
Tables 1-63 through 1-68. 1-69, 1-70, 1-75, 1-76, 1-81, 1-82, Tables 1-87 through 1-92,
Tables 1-99, 1-100, 1-107, and 1-108.
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Updated the C VREFTB value in Table 1-9.
Updated Table 1-21.
Under “High-Speed I/O Specification” section, updated Tables 1-25 through 1-30.
Updated Tables 1-31 through 1-38.
Added new Table 1-32.
October 2007
1.4
■
Under “Maximum Input and Output Clock Toggle Rate” section, updated Tables 1-40
through 1-42.
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Under “IOE Programmable Delay” section, updated Tables 1-43 through 1-44.
Under “User I/O Pin Timing Parameters” section, updated Tables 1-45 through 1-92.
Under “Dedicated Clock Pin Timing Parameters” section, updated Tables 1-93 through 1-
108.
Updated Table 1-1 with V ESDHBM and V ESDCDM information.
Updated R CONF_PD information in Tables 1-10.
July 2007
1.3
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Added Note (3 ) to Table 1-12.
Updated t DLOCK information in Table 1-19.
Updated Table 1-43 and Table 1-44.
Added “Document Revision History” section.
June 2007
1.2
Updated Cyclone III graphic in cover page.
July 2012
Altera Corporation
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| DK-DEV-4S100G5N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For EP4S100G5F RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
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