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| 型号： | DK-DEV-3CLS200N |
| 厂商： | Altera |
| 文件页数： | 5/34页 |
| 文件大小： | 0K |
| 描述： | KIT DEV CYCLONE III LS EP3CLS200 |
| 产品培训模块： | Cyclone® III FPGA Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3CLS200 |
| 所含物品： | 板 |
| 产品目录页面： | 606 (CN2011-ZH PDF) |
| 相关产品： | 544-2564-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2563-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2562-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2561-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2560-ND - IC CYCLONE III FPGA 5K 256 UBGA 544-2559-ND - IC CYCLONE III FPGA 5K 164 MBGA 544-2558-ND - IC CYCLONE III FPGA 5K 256 FBGA 544-2557-ND - IC CYCLONE III FPGA 5K 144 EQFP 544-2556-ND - IC CYCLONE III FPGA 55K 484 UBGA 544-2554-ND - IC CYCLONE III FPGA 55K 780 FBGA 更多... |
| 其它名称： | 544-2601 |
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Chapter 1: Cyclone III Device Datasheet
1–5
Electrical Characteristics
DC Characteristics
This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT)
tolerance, and bus hold specifications for Cyclone III devices.
Supply Current
Standby current is the current the device draws after the device is configured with no
inputs or outputs toggling and no activity in the device. Use the Excel-based early
power estimator (EPE) to get the supply current estimates for your design because
these currents vary largely with the resources used. Table 1–4 lists I/O pin leakage
current for Cyclone III devices.
Handbook .
Symbol
I I
I OZ
Parameter
Input pin leakage current
Tristated I/O pin leakage
current
Conditions
V I = 0 V to V CCIOMAX
V O = 0 V to V CCIOMAX
Min
–10
–10
Typ
—
—
Max
10
10
Unit
? A
? A
(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all
V CCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).
(2) 10 ? A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the
observed when the diode is on.
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 1–5. Cyclone III Devices Bus Hold Parameter
(Part 1 of 2)
V CCIO (V)
Parameter
Condition
1.2
1.5
1.8
2.5
3.0
3.3
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold
low,
sustaining
V IN > V IL
(maximum)
8
—
12
—
30
—
50
—
70
—
70
—
? A
current
Bus-hold
high,
sustaining
V IN < V IL
(minimum)
–8
—
–12
—
–30
—
–50
—
–70
—
–70
—
? A
current
July 2012
Altera Corporation
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