
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
191 of 366
11.4.6 CPU Queues
The pools and queue referred to in this section are shown in the block diagram in
Figure 10-49. Whenever a queue
or pool level exceeds the associated threshold register, a latched status bit is set in the
CPU_Queues_changeregister which generates an interrupt unless masked by the associated mask bit in the
CPU_Queues_maskregister.
In this section the address offsets in parentheses apply when the CPU data bus is 16 bits wide (pin
). The base address for the TDMoP CPU queues is 0x20,000.
Table 11-7. CPU Queues
Addr
Offset
Register Name
Description
Page
0x00 (0x02)
Write to insert a buffer ID into the TDM-to-CPU Pool
0x04 (0x06)
Number of buffers stored in the TDM-to-CPU Pool
0x08 (0x0A)
TDM-to-CPU Pool interrupt threshold
3
Read to get a buffer ID from the TDM-to-CPU Queue
0x10 (0x12)
Number of buffers in the TDM-to-CPU Queue
0x14 (0x16)
TDM-to-CPU Queue interrupt threshold
0x18 (0x1A)
Write to insert a buffer ID into the CPU-to-ETH Queue
0x1C (0x1E)
Number of buffers in the CPU-to-ETH Queue
0x20 (0x22)
0x24 (0x26)
Write to insert a buffer ID into the ETH-to-CPU Pool
0x28 (0x2A)
Number of buffers stored in the ETH-to-CPU Pool
0x2C (0x2E)
0x30 (0x32)
Read to get a buffer ID from the ETH-to-CPU Queue
0x34 (0x36)
Number of buffers in the ETH-to-CPU Queue.
0x38 (0x3A)
0x54 (0x56)
Write to insert a buffer ID into the CPU-to-TDM Queue
Error!
Bookmark
not defined.
0x58 (0x5A)
Number of buffers stored in the CPU-to-TDM Queue
Error!
Bookmark
not defined.
0x5C (0x5E)
0x60 (0x62)
0x64 (0x66)
Number of buffers stored in the CPU-Tx-return Queue
0x68 (0x6A)
CPU-Tx-return Queue interrupt threshold
0x6C (0x6E)
Read to get a buffer ID from the CPU-Rx-return Queue
0x70 (0x72)
Number of buffers stored in the CPU-Rx-return Queue
0x74 (0x76)
CPU-Rx-return Queue interrupt threshold
11.4.6.1 TDM-to-CPU Pool
TDM_to_CPU_pool_insert 0x00 (0x02)
Bits
Data Element Name
R/W
Reset
Value
Description
[31:13]
Reserved
-
0x0
Must be set to zero
[12:0]
Buffer ID
WO
None
Writing to this address causes a single 13-bit buffer ID to
be inserted to the TDM-to-CPU pool. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to
H_AD[23:11]
out of the 24 SDRAM address bits).