
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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9 PIN DESCRIPTIONS
9.1 Short Pin Descriptions
Table 9-1. Short Pin Descriptions
TYPE
PIN DESCRIPTION
Internal E1/T1 LIU Line Interface
I
LIU Transmit Enable Input (for all LIUs)
Oa
LIU Transmitter Analog Outputs
Ia
LIU Receiver Analog Inputs
I
Receive Termination Selection Input (for All LIUs)
I
Reference Resistor for LIU Analog Circuits (precision 10k
to ARVSS)
External E1/T1 LIU Interface
O
Transmit Clock Output
O
Transmit Data Output
IO
Receive Clock Input to Framer (RCLKFn)
or Recovered Clock Output from LIU Receiver (RCLKn)
I
Receive Data Input to Framer
Framer TDM Interface
I
Transmit Clock Input to Formatter
I
Transmit System Clock Input (clock for cross-connect side of elastic store)
or External Reference Clock Input
I
Transmit Serial Data Input
IO
Transmit Frame/Multiframe Sync Input/Output or Transmit System
Frame/Multiframe Sync Input (sync for cross-connect side of elastic store)
I
Receive System Clock Input (clock for cross-connect side of elastic store)
O
Receive Serial Data Output
IO
Receive Frame/Multiframe Sync Input/Output
O
Receive Frame Sync or Receive Multiframe Sync Output
O
Receive Loss of Frame Output or Receive Loss of Signal Output
TDM-over-Packet Engine TDM Interface
O
TDMoP Recovered Clock Output
Ipu
TDMoP Transmit Clock Input (here transmit means “toward LIU”)
O
TDMoP Transmit Data Output
Ipd
TDMoP Transmit Frame Sync Input
IOpd
TDMoP Transmit Multiframe Sync Input or Carrier Detect Output
O
TDMoP Transmit Signaling Output or Clear to Send Output
Ipu
TDMoP Receive Clock Input (here receive means “toward Ethernet MII”)
Ipu
TDMoP Receive Data Input
Ipd
TDMoP Receive Frame/Multiframe Sync Input
Ipu
TDMoP Receive Signaling Input or Request To Send Input
SDRAM Interface
O
SDRAM Clock
IO
SDRAM Data Bus
O
SDRAM Byte Enable Mask
O
SDRAM Address Bus
O
SDRAM Bank Select Outputs
O
SDRAM Chip Select (Active Low)
O
SDRAM Write Enable (Active Low)
O
SDRAM Row Address Strobe (Active Low)
O
SDRAM Column Address Strobe (Active Low)
Ethernet PHY Interface (MII/RMII/SSMII)
I
MII Transmit Clock Input
O
SSMII Transmit Clock Output
O
MII Transmit Data Outputs
O
MII Transmit Enable Output
O
MII Transmit Error Output