参数资料
型号: IBM21P100BGB
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封装: 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件页数: 117/140页
文件大小: 2032K
代理商: IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 70 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
5.2.5.12 Opaque Memory Enable Register
The Opaque Memory Enable register enables the Opaque Memory Base, Opaque Memory Limit, Opaque
Memory Base Upper 32 Bits, and the Opaque Memory Limit Upper 32 Bits registers. These registers specify
a range of 64-bit memory addresses that are used exclusively on the secondary PCI bus and are not to be
accepted by the bridge on either the primary or secondary interfaces.
Address Offset
x‘70’
Access
Read/Write
Reset Value
x‘00’
When OPAQUE_EN (pin AA18) is tied low. See
ping Pins and Other Signals on page 99 for details of strapping consider-
ations.
Reset Value
x‘01’
When OPAQUE_EN (pin AA18) is tied high. See
ping Pins and Other Signals on page 99 for details of strapping consider-
ations.
Res
e
rv
ed
O
paque
M
e
m
o
ry
Enable
7654321
0
Bit(s)
Access
Field Name and Description
7:1
RO
Reserved
0RW
Opaque Memory Enable
0
Disable the opaque memory address range
1
Enable the opaque memory address range
This bit is reset according to the tie value of module pin AA18, OPAQUE_EN.
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