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| 型号： | IBM21P100BGB |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件页数： | 62/140页 |
| 文件大小： | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Bus Operation
Page 20 of 131
ppb11_operations.fm.03
July 9, 2001
3.3.5.2 Algorithm for PCI-to-PCI-X Mode
The algorithm for transfers in this mode is much the same as for transfers in PCI-to-PCI mode, except that the
maximum request amount may be additionally constrained by the setting of the split transaction commitment
limit value in the Upstream or Downstream Split Transaction register. The only other difference is that
prefetching will not cease when the originating master disconnects. Prefetching will only cease when all of the
requested data is received, as required by the PCI-X architecture.
The setting of the enable relaxed ordering bit will set the relaxed ordering bit in the read data request on the
PCI-X interface.
3.3.5.3 Algorithm for PCI-X-to-PCI and PCI-X-to-PCI-X Mode
The algorithm for transfers in these modes is to transfer the amount of requested data.
In PCI-X-to-PCI mode the bridge keeps requesting the PCI interface and keeps the prefetch buffer full until
the entire request amount is transferred.
In PCI-X to PCI-X mode the algorithm is controlled by the split transaction commitment limit value contained
in the Upstream or Downstream Split Transaction register. If the value is greater than or equal to the split
transaction capacity (4KB) but less than 32KB, the maximum request amount is 512 bytes. Hence, larger
transfers will be decomposed into a series of smaller transfers, until the original byte count has been satisfied.
If the commitment limit value indicates 32KB or more, the original request amount is used and decomposition
is not performed.
If the original request is broken into smaller requests the bridge waits until the previous completion has been
totally received before a new request is issued. This ensures that the data does not get out of order and that
two requests with the same sequence ID are not issued. In any case, the bridge generates a new requester
ID for each request passed through the bridge.
3.4 Configuration Transactions
The
PCI Local Bus Specification defines two configuration transaction types, Type 0 and Type 1. These two
configuration formats are distinguished by the value of bus address bits (1:0). If address bits (1:0) are b‘00’
during a configuration transaction, a Type 0 configuration transaction is being indicated. A Type 0 configura-
tion transaction is used to access configuration information for devices on the current bus segment. A Type 0
configuration transaction is not forwarded across the bridge, but rather is used to configure the bridge itself. If
address bits (1:0) are b‘01’ during a configuration transaction, a Type 1 configuration transaction is being indi-
cated. Type 1 configuration transactions are used to access devices that reside behind one or more bridges.
Figure 2 shows the address formats for Type 0 and Type 1 configuration transactions:
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