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| 型号： | IBM21P100BGB |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件页数： | 138/140页 |
| 文件大小： | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_clock_reset.fm.03
July 9, 2001
Clocking and Reset
Page 89 of 131
Since the internal PLL is bypassed in PCI mode and the S_CLK input is used directly, the IBM 133 PCI-X
Bridge R1.1 has no need to distinguish between the PCI 66 and PCI 33 modes. Therefore the bridge does not
an I/O pin for the M66EN signal on its secondary interface. However, as stated in the architecture, the system
designer should bus this signal to all devices on the bus in case the other clients require it.
6.4 Clock Stability
The PCI / PCI-X architectures specify that the bus clock must be stable and running at its designated
frequency for at least 100
ms prior to the de-assertion of the bus reset signal. As the IBM 133 PCI-X Bridge
R1.1 does not generate the secondary bus clock but does control the secondary bus reset signal, it must be
aware of when its S_CLK input has become stable in order to meet this requirement. For this purpose, an
input signal labelled S_CLK_STABLE is provided. During a bus reset, the bridge will wait for the assertion of
S_CLK_STABLE before doing the mode and frequency determination sequence described in Section 6.3.2
There are several possibilities for the source of the S_CLK_STABLE input signal. Some clock generation
circuits that utilize phase-locked loops provide a “lock” indicator that may be used for this purpose. Care must
be taken, however, to assure that the lock indicator does not toggle randomly while the PLL is locking to the
desired frequency, before reaching a steady state -- the bridge is expecting at most one transition on this
input from the “not stable” to the “stable” state. Another possibility is to tie-up the signal, if one can guarantee
that the secondary clock input will always be stable prior to the de-assertion of the primary bus reset signal or
the Secondary Bus Reset bit of the Bridge Control register (see Section 6.6.2 on page 91). This may be the
Figure 3: Programmable Pull-up Circuit
3.3V
S_PCIXCAP
S_PCIXCAP_PU
Weak
Pull-up
Strong
Pull-up
For PCI-X
66 MHz Cards
For PCI-X
100/133 MHz Cards
For PCI
Cards
S_SEL100
3.3V
For 100 MHz
For 133 MHz
Enabled During
Bus Capability
Determination
IBM 133 PCI-X Bridge R1.1
10k
W
0.01mF
56k
W
10k
W
1k
W
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