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| 型号： | IBM21P100BGB |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件页数： | 58/140页 |
| 文件大小： | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Bus Operation
Page 16 of 131
ppb11_operations.fm.03
July 9, 2001
The bridge attempts to transfer write data on the conventional PCI interface as soon as a 128-byte boundary
is crossed or the end of the PCI-X transfer occurs, whichever comes first. As long as a 128-byte buffer or the
end of transfer remains from the PCI-X memory write command when a 128-byte boundary is crossed, the
transfer will continue on the conventional PCI interface.
3.2.1.3 PCI to PCI Transactions
When both buses are operating in conventional PCI mode, the bridge passes the memory write command
that it receives to the destination interface, unless the bridge is disconnected in the middle of a memory write
and invalidate and is not on a cache line boundary. In this event, the command will continue as a memory
write when the bridge attempts to reconnect.
The bridge attempts to transfer a memory write command as soon as the transaction ends or a 128-byte
boundary is crossed, whichever comes first. As long as a 128-byte buffer or the end of transfer remains from
the PCI memory write command when a 128-byte boundary is crossed, the transfer will continue.
3.2.1.4 PCI-X to PCI-X Transactions
When both buses are operating in PCI-X mode, the bridge passes the memory write command that it
receives to the destination interface along with the originating byte count and transaction ID.
The bridge attempts to transfer a memory write command as soon as the transaction ends or a 128-byte
boundary is crossed, whichever comes first. As long as a 128-byte buffer or the end of transfer remains from
the PCI-X memory write command when a 128-byte boundary is crossed, the transfer will continue.
If a transaction is disconnected on the destination interface in the middle of a continuing transfer, the byte
count and address are updated and the transaction is presented again on the destination interface. If a trans-
action is disconnected in the middle of a continuing transfer on the originating interface, the originator must
present the transaction again with the updated byte count and address.
3.2.2 Delayed/Split Write Transactions
I/O writes and Type 1 configuration writes are treated as delayed transactions in the bridge. These
commands will be retried on the originating bus, completed on the destination bus, and then completed on
the originating bus. The bridge executes DWord transactions only as delayed transactions in conventional
PCI mode and as split requests in PCI-X mode.
There is only one request queue entry for either delayed or split write transactions.
3.2.3 Immediate Write Transactions
Type 0 configuration writes on the primary PCI interface meant for the bridge are treated as an immediate
write transaction by the bridge. The bridge executes the transaction and indicates its completion by accepting
the DWord of data immediately.
3.3 Read Transactions
Read transactions are treated as either delayed (PCI), split (PCI-X), or immediate read transactions, as
shown in
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