
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Configuration Registers
Page 76 of 131
ppb11_pcix_regs.fm.03
July 9, 2001
4RW
Split Completion Overrun
This bit is set if the bridge terminates a Split Completion on the secondary bus with Retry or Disconnect at
Next ADB because the bridge buffers are full. It is used by algorithms that optimize the setting of the down-
stream Split Transaction Commitment Limit register.
0
bridge has accepted all Split Completions
1
bridge has terminated a Split Completion with Retry or Disconnect at Next ADB because bridge
buffers were full.
3RW
Unexpected Split Completion
This bit is set if an unexpected Split Completion with a Requester ID equal to the bridge’s secondary bus
number, device number x‘00’, and function number 0 is received on the bridge’s secondary interface.
0
no unexpected Split Completion has been received
1
an unexpected Split Completion has been received
2RW
Split Completion Discarded
This bit is set if the bridge discards a Split Completion moving toward the secondary bus because the
requester would not accept it.
0
no Split Completion has been discarded
1
a Split Completion has been discarded
1RO
133 MHz Capable
This bit is read-only and is a b‘1’ indicating that this bridge is capable of 133 MHz operation on the second-
ary interface.
0RO
64-bit Device
This bit is read-only and is a b‘1’ indicating that the width of the bridge’s secondary AD interface is 64 bits.
Bit(s)
Access
Field Name and Description