
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 73 of 131
5.2.5.16 Opaque Memory Limit Upper 32 Bits Register
The Opaque Memory Limit Upper 32 Bits register specifies upper address bits 63:32 of the opaque memory
address range. It is used in conjunction with the Opaque Memory Base register, the Opaque Memory Limit
register, and the Opaque Memory Base Upper 32 Bits register to specify a range of 64-bit addresses that are
used exclusively on the secondary bus. These memory addresses will not be accepted by the bridge on the
primary or the secondary buses. This address range is enabled by bit 0 of the Opaque Memory Enable
register.
5.2.5.17 PCI-X ID Register
The PCI-X ID register identifies this register set in the Capabilities List as a PCI-X register set. It is read-only,
returning x‘07’ when read.
Address Offset
x‘7C’
Access
Read/Write
Reset Value
x‘FFFF FFFF’
Opaque Memory Limit Upper 32 Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
31:0
RW
Opaque Memory Limit Upper 32 Bits
Address bits 63:32 of the limit address for the opaque memory address range. Memory operations in this range
are not accepted by the bridge on either the primary or secondary interfaces.
Address Offset
x‘80’
Access
Read only
Reset Value
x‘07’
PCI-X Capability ID
7654321
0
Bit(s)
Access
Field Name and Description
7:0
RO
PCI-X Capability ID
Returns x‘07’ when read indicating that this register set of the Capabilities List is a PCI-X register set.