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参数资料
| 型号： | IBM21P100BGB |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304 |
| 文件页数： | 51/140页 |
| 文件大小： | 2032K |
| 代理商： | IBM21P100BGB |
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IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
General Information
Page 10 of 131
ppb11_intro.fm.03
July 9, 2001
2.5 Operation Overview
This section gives a brief description of various aspects of IBM 133 PCI-X Bridge R1.1 operation. More
detailed information on these topics can be found in subsequent chapters.
2.5.1 Supported Modes
The IBM 133 PCI-X Bridge R1.1 is a full-function transparent PCI-X to PCI-X bridge. As such, either interface
may be configured to operate using the conventional PCI bus protocol or the PCI-X bus protocol. In mixed-
mode configurations, IBM 133 PCI-X Bridge R1.1 hardware handles the conversion from one protocol to the
other.
Any allowed bus clock frequency range for a particular mode may be used, up to 66 MHz for PCI mode and
up to 133 MHz per section 9.4.1 of the PCI-X 1.0a specification. Operation at a particular speed depends on
the bus topology and loading. Since the two clock domains are asynchronous and independent, a different
bus speed may be used on each interface. Speed-matching is accomplished via the robust buffering structure
of the IBM 133 PCI-X Bridge R1.1 design.
While the IBM 133 PCI-X Bridge R1.1 implements a 64-bit bus on both interfaces, the PCI architecture allows
either side to be connected to a 32-bit bus or to 32-bit devices. Full 64-bit addressing capability is also
provided, including support for Dual Address Cycles.
The IBM 133 PCI-X Bridge R1.1 uses the 3.3 V signaling environment and is
not tolerant of 5 V signal levels.
When IBM 133 PCI-X Bridge R1.1 is mounted on an adapter card, the card must use the 3.3 V connector
keying scheme.
2.5.2 Buffer Structure
The IBM 133 PCI-X Bridge R1.1 contains two symmetric sets of buffers with associated queues, one for
upstream transactions and the other for downstream transactions.
2.5.2.1 Burst Read Buffers
Each burst read buffer contains 4 KB to hold data from memory burst read transactions. Each buffer is logi-
cally divided into eight independent 512-byte buffers to allow for multi-threading. Hence, the read queues
have eight entries, and up to eight active read transactions in each direction are possible.
Every 512-byte buffer is further divided into four 128-byte subsections. In general, activity occurs in the bridge
on these 128-byte boundaries; that is, filling and/or emptying 128 bytes causes bus transactions to be initi-
ated. While each read queue entry has at most 512 bytes of buffer space associated with it, the design re-
uses the 128-byte subsections as needed once they are emptied, to keep data flowing efficiently. This means
that in the case where the primary and secondary interfaces are running at similar frequencies and there is
little bus contention, long transfers can proceed without disconnection after the initial latency needed to fill the
first 128-byte subsection. Conversely, for large transfers when the two buses are running at vastly dissimilar
frequencies, disconnects may occur as often as every 128 bytes on the faster bus as the 512-byte buffer
becomes completely full or empty.
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