参数资料
型号: IBM21P100BGB
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封装: 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件页数: 118/140页
文件大小: 2032K
代理商: IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 71 of 131
5.2.5.13 Opaque Memory Base Register
The Opaque Memory Base register specifies base address bits 31:20 of the opaque memory address range.
It is used in conjunction with the Opaque Memory Limit register, the Opaque Memory Base Upper 32 Bits
register, and the Opaque Memory Limit Upper 32 Bits register to specify a range of 64-bit memory addresses
that are used exclusively on the secondary bus. These memory addresses will not be accepted by the bridge
on the primary or the secondary buses. This address range is enabled by bit 0 of the Opaque Memory Enable
register. Bits 19:0 of the base address are assumed to be x‘0 0000’. This register also specifies that the
bridge supports 64-bit opaque memory addressing.
Address Offset
x‘74’
Access
See individual fields
Reset Value
x‘0001’
Opaque Memory Base Address
64-bit
addressing
15 14 13 12 11 10
9
876543210
Bit(s)
Access
Field Name and Description
15:4
RW
Opaque Memory Base Address
Address bits 31:20 of the base address for the opaque memory address range. Memory operations in this
range are not accepted by the bridge on either the primary or secondary interfaces.
3:0
RO
64-bit addressing
Set to b‘0001’ to indicate support of 64-bit addressing.
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