参数资料
型号: IBM21P100BGB
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PBGA304
封装: 31 X 31 MM, HEAT SINK, PLASTIC, BGA-304
文件页数: 90/140页
文件大小: 2032K
代理商: IBM21P100BGB
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
ppb11_pcix_regs.fm.03
July 9, 2001
Configuration Registers
Page 45 of 131
5.2.4.17 I/O Limit Register
The I/O Limit register specifies the upper address of the I/O address range bits 15:12 and is used in conjunc-
tion with the I/O Base register and I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits to specify a range of
32-bit addresses supported for I/O transactions on the PCI Bus. Address bits 11:0 are assumed to be x‘FFF’
for the limit address. This register also specifies that the bridge supports 32-bit I/O addressing.
Address Offset
x‘1D’
Access
See individual fields
Reset Value
x‘X1’
I/O Limit
Addressing
32-Bit
Addressing
7654
3210
Bit(s)
Access
Field Name and Description
7:4
RW
I/O Limit Address
Address bits 15:12 of the limit address for the address range of I/O operations that are passed from the primary
to the secondary PCI bus.
3:0
RO
Set to b‘0001’ to indicate that 32-bit I/O addressing is supported.
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