
IBM21P100BGB
IBM 133 PCI-X Bridge R1.1
Clocking and Reset
Page 94 of 131
ppb11_clock_reset.fm.03
July 9, 2001
6.9 Secondary Device Masking
The IBM 133 PCI-X Bridge R1.1 supports the masking of secondary devices through configuration/power
strapping of the Secondary Bus Private Device Mask register. The process of converting Type 1 configuration
transactions to Type 0 configuration transactions is modified by the contents of the Secondary Bus Private
Device Mask register. A configuration transaction that targets a device masked by this register is reouted to
device 15.Secondary bus architectures which are designed to support masking of devices should not imple-
ment a device number 15 (i.e., S_AD(31)).
The device mask bit options (device numbers 1, 4, 5, 6, 7, 9, and 13) defined by the bridge allow architectures
to support private device groupings that use a single or multiple interrupt binding per table 9-1 of the
PCI-to-PCI Bridge specification.
6.10 Handling of Address Phase Parity Errors
When an address parity error is detected by the bridge, the transaction will not be claimed (by not asserting
DEVSEL#) and is allowed to terminate with a Master-Abort. The bridge will detect address parity errors for all
transactions on both the primary and secondary interfaces. The result of an address parity error will be
controlled by the parity error response bits in both the Command register and the Bridge Control register.