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参数资料
| 型号： | IBM21P100BGC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件页数： | 110/144页 |
| 文件大小： | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Configuration Registers
Page 68 of 144
ppb20_pcix_regs.fm.01
October 15, 2001
11
RW
Enable Relaxed Ordering
For a read operation, this bit enables read completions that occur after the first read completion to bypass
posted writes and complete with a higher priority. Only read completions being presented on the primary
interface are affected by this bit.
0
Conventional mode, read command relaxed ordering disabled: each target bus read completion
transaction will be ordered with posted writes in the opposite direction (traveling the same direction
as the completion data). see the PCI Bridge Specification 2.0, Table 5-2.
1
Conventional mode, read command relaxed ordering enabled: only the first read completion of a
read transaction will be required to meet the PCI ordering requirement for delayed read completion
vs. posted writes (PCI Bridge Specification 2.0, Table 5-2) all subsequent read completions for the
same master transaction will be allowed to pass posted writes in the opposite direction.
This bit is used only for requests issued in the PCI mode. For requests issued in the PCI-X mode the relaxed
ordering bit in the attribute field takes precedence.
10
RW
Secondary Special Delayed Read Mode Enable bit
Allows a secondary master to change the memory read command (MR, MRL, or MRM) code after it has
received retry to another memory read command (MR, MRL, or MRM) code.
0
Retry any secondary master which repeats its transaction with command code changes.
1
Completed a MR, MRL, or MRM transaction on the secondary bus and the initiator (or another)
master on the secondary bus initiates a MR, MRL, or MRM transaction with the same address and
byte enables, then the bridge will complete it normally.
This bit is ignored when the secondary interface is in the PCI-X mode.
9:8
RW
Secondary Read prefetch mode bits
Controls prefetching for memory read transactions, that are initiated on the secondary bus.
00
One cache line prefetch.
01
Reserved.
10
Full prefetch.
11
No prefetching, full handshake between initiator and target. Disconnect on first DWord.
These bits are ignored when the secondary interface is in the PCI-X mode.
7:6
RW
Secondary Read Line prefetch mode bits
Controls prefetching for memory read line transactions, that are initiated on the secondary bus.
00
One cache line prefetch.
01
Reserved.
10
Full prefetch.
11
Reserved.
These bits are ignored when the secondary interface is in the PCI-X mode.
5:4
RW
Secondary Read Multiple prefetch mode bits
Controls prefetching for memory read multiple transactions that are initiated on the secondary bus.
00
One cache line prefetch.
01
Reserved.
10
Full prefetch.
11
Reserved.
These bits are ignored when the secondary interface is in the PCI-X mode.
3:0
RO
Reserved.
Bit(s)
Access
Field Name and Description
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相关代理商/技术参数 |
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