- 您现在的位置：买卖IC网 > PDF目录67681 > IBM21P100BGC PCI BUS CONTROLLER, PBGA304 PDF资料下载
参数资料
| 型号： | IBM21P100BGC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件页数： | 64/144页 |
| 文件大小： | 5197K |
| 代理商： | IBM21P100BGC |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页当前第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
Bus Operation
Page 26 of 144
ppb20_operations.fm.01
October 15, 2001
The bridge translates a PCI-X memory read block command into one of three conventional PCI memory read
commands based on the byte count and starting address. If the starting address and byte count are such that
only a single DWord (or less) is being read, the conventional transaction uses the memory read command. If
the PCI-X transaction reads more than one DWord, but does not cross a cache line boundary (as indicated by
the Cache Line Size register in the conventional Configuration Space header), the conventional transaction
uses the memory read line command. If the PCI-X transaction crosses a cache line boundary, the conven-
tional transaction uses the memory read multiple command.
If a disconnect occurs before the byte count of the PCI-X memory read block command is exhausted, the
bridge continues to issue the command until all the bytes in the count are received. The bridge disconnects
once the buffer is filled and prefetches more data as 128-byte sectors of the buffer become free when split
completion data is returned to the originator, until the byte count is exhausted.
3.3.1.3 PCI to PCI Transactions
This mode does not involve any translation.
If the memory read command targets non-prefetchable memory space, the memory read fetches only the
requested double word. Bits 9:8 of the primary and secondary data buffering control registers control the
prefetching algorithm for the memory read command in prefetchable space. The default value of these bits
indicates that up to one cache line will be prefetched.
For the memory read line command, the prefetching algorithm is controlled by bits 7:6 of the primary and
secondary data buffering control registers. The default value of these bits indicates that up to one cache line
will be prefetched.
For the memory read multiple command, the prefetching algorithm is controlled by bits 5:4 of the primary and
secondary data buffering control registers. The default value of these bits indicates that a full prefetch will be
done, subject to the limit imposed by the maximum memory read byte count value set by bits (14:12) of the
same register. The default value is 512 bytes or an entire read buffer. Data fetching operations will be discon-
nected at all 1 MB boundaries.
3.3.1.4 PCI-X to PCI-X Transactions
This mode does not involve any translation.
The amount of data that is fetched is controlled by the downstream and upstream split transaction control
register. The split transaction capacity and split transaction commitment limit fields control how much data is
requested at any one time.
3.3.2 I/O Read
The I/O Read command is not translated and fetches a DWord of data. The command will either be split in the
PCI-X mode or delayed in the conventional PCI mode.
3.3.3 Configuration Read
3.3.3.1 Type 1 Configuration Read
The Type 1 configuration read command is only accepted on the primary interface. The command will either
be split in the PCI-X mode or delayed in the conventional PCI mode.
相关PDF资料 |
PDF描述 |
|---|---|
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| IBM25EMPPC740LDBC4000 | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
发布紧急采购，3分钟左右您将得到回复。