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| 型号： | IBM21P100BGC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件页数： | 17/144页 |
| 文件大小： | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_signals.fm.01
October 15, 2001
Signal Descriptions
Page 113 of 144
7.3 Strapping Pins and Other Signals
Table 7-3. List of Strapping Pins and Other Signals (Page 1 of 2)
Signal Name
I/O
Width
Description
64_BIT_DEVICE#
I
1
Physical bus width of the PCI-X device
Used only when the IBM 133 PCI-X Bridge R2.0 is employed as the bus interface on a
PCI-X add-in card. The PCI-X Specification requires that such devices indicate the phys-
ical width of their bus in bit 16 of the PCI-X bridge status register. Bit 16 of the PCI-X
bridge status register is set directly from the inverse of the 64_BIT_DEVICE# pin. This
information is used solely by the configuration software; operation of the IBM 133 PCI-X
Bridge R2.0 is unaffected.
0
bit 16 of the PCI-X bridge status register is set to b’1’, indicating a 64 bit bus.
1
bit 16 of the PCI-X bridge status register is set to b’0’, indicating a 32 bit bus.
BAR_EN
I
1
Base Address Register Enable
Used to enable the base address register at reset or power up. The 64 bit register
located at offsets x'10' and x'14' is used to claim a 1 MB memory region when enabled.
The register returns all zeroes to read accesses and the associated memory region is
not claimed when disabled.
0
BAR disabled, register reads returns 0’s, no memory region claimed.
1
BAR enabled, bits 63:20 can be written by software to claim a 1 MB memory
region.
IDSEL_REROUTE_EN
I
1
IDSEL Reroute Enable
Used to enable the IDSEL reroute function at reset or power up. The reset value of the
secondary bus private device mask register is modified according to the tie value of the
IDSEL_REROUTE_EN pin. Note that configuration software can subsequently modify
the secondary bus private device mask register, regardless of how the
IDSEL_REROUTE_EN pin is tied.
0
reset value of the secondary bus private device mask register is x’00000000’.
1
reset value of the secondary bus private device mask register is x’22F20000’.
OPAQUE_EN
I
1
Opaque Region Enable
Used to enable the opaque memory region at reset or power up. The reset value of bit 0
of the opaque memory enable register is modified according to the tie value of the
OPAQUE_EN pin. The configuration software can subsequently modify bit 0 of the
opaque memory enable register, regardless of how the OPAQUE_EN pin is tied.
0
reset value of bit 0 of the opaque memory enable register is b’0’.
1
reset value of bit 0 of the opaque memory enable register is b’1’.
P_CFG_BUSY
I
1
Primary Configuration Busy
Controls the reset and power up value of bit 2 of the miscellaneous control register.
Used to sequence initialization with regard to the primary and secondary buses for appli-
cations that require access to the bridge configuration registers from the secondary bus.
When pulled high, the configuration commands received on the primary bus are retried
until such time as bit 2 of the miscellaneous control register is set to b‘0’ by a configura-
tion write initiated from the secondary bus. Applications that do not require access to the
bridge configuration registers from the secondary bus should pull this signal to ground.
0
reset value of bit 2 of the miscellaneous control register is b‘0’.
1
reset value of bit 2 of the miscellaneous control register is b‘1’.
P_DRVR_MODE
I
1
Primary driver mode control
Used to alter the output impedance of the primary bus PCI/PCI-X drivers, to account for
how many drops are on the bus. This line should be pulled through a resistor to a high or
a low as needed. Internal pull down.
0
use the default impedance value.
1
select the alternate impedance value.
RESERVED2
1
Reserved pin
RESERVED2 should be pulled to ground.
Note: Each strapping pin or reserved pin should have an unshared series resistor tying it to either ground or 3.3 V. The value of the
resistor may be selected to limit part number count, but the value should be greater than or equal to 100
and less than or equal to 5k.
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