
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_pcix_regs.fm.01
October 15, 2001
Configuration Registers
5.2.5.8 Primary Retry Counter Register
This register defines the number of retries that the bridge receives on the secondary bus for a requested
transaction, before its internal retry counter expires. When the counter expires, the bridge discards the
request, and, if enabled, will issue SERR# on the primary bus.
This mechanism prevents deadlock when the target is unable to receive the request, and allows recovery
through the use of SERR#.
The only allowed values are:
x‘0000 0000’: Counting disabled (No expiration)
x‘0000 0100’: 256 retries before expiration
x‘0001 0000’: 64K retries before expiration
x‘0100 0000’: 16M retries before expiration
x‘8000 0000’: 2G retries before expiration
Address Offset
x‘60’
Access
Read/Write
Reset Value
x‘0000 0000’
Restrictions
Only one bit can be set at any time, setting multiple bits results in the smaller retry
count.
2G
re
tr
ie
s
Reserved
16
M
ret
ri
e
s
Reserved
64
K
re
tr
ies
Reserved
25
6
ret
ri
es
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Bit(s)
Access
Field Name and Description
31
RW
This bit used to indicate 2G retries before expiration.
30:25
RO
Reserved.
24
RW
This bit used to indicate 16M retries before expiration.
23:17
RO
Reserved.
16
RW
This bit used to indicate 64K retries before expiration.
15:9
RO
Reserved.
8
RW
This bit used to indicate 256 retries before expiration.
7:0
RO
Reserved.