- 您现在的位置：买卖IC网 > PDF目录67681 > IBM21P100BGC PCI BUS CONTROLLER, PBGA304 PDF资料下载
参数资料
| 型号： | IBM21P100BGC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件页数： | 65/144页 |
| 文件大小： | 5197K |
| 代理商： | IBM21P100BGC |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页当前第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页
IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_operations.fm.01
October 15, 2001
Bus Operation
Page 27 of 144
3.3.3.2 Type 0 Configuration Read
The Type 0 configuration read command is accepted on either the primary or secondary interface. The
command returns immediate data on the primary interface regardless of the interface mode. On the
secondary interface the command is treated as a delayed transaction in the PCI mode and as a split transac-
tion in the PCI-X mode.
3.3.4 Non-Prefetchable and DWord Reads
A non-prefetchable read transaction is a read transaction in which the bridge requests exactly one DWord
from the target and disconnects the initiator after delivering that one DWord of read data. Unlike prefetchable
read transactions, the bridge forwards the read byte enable information for the data phase.
Non-prefetchable behavior is used for I/O, configuration, memory read transactions that fall into the non-
prefetchable memory space for PCI mode, and all DWord read transactions in PCI-X mode.
3.3.5 Prefetchable Reads
A prefetchable read transaction is a read transaction where the bridge performs speculative reads, transfer-
ring data from the target before it is requested from the initiator. This behavior allows a prefetchable read
transaction to consist of multiple data transfers. For prefetchable read transactions, all byte enables are
asserted for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for
memory read transactions that fall into prefetchable memory space and are allowed to fetch more than a
DWord. The amount of data that is prefetched depends on the type of transaction and the setting of bits in the
primary and secondary data buffering control registers in configuration space. The amount of prefetching may
also be affected by the amount of free buffer space available in the bridge, and by any read address bound-
aries encountered. Examples of these boundaries are cache line for cache line reads and 1M address
boundary to ensure that a read does not cross into another devices’ space.
3.3.5.1 Algorithm for PCI-to-PCI Mode
The algorithm used for transfers in PCI-to-PCI mode is user defined in the primary and secondary data buff-
ering control registers. These registers have bits for memory read to prefetchable space, memory read line,
and memory read multiple transactions. For memory read, the bits select whether to read a DWord, read to a
cache line boundary, or to fill the prefetch buffer. For memory read line and memory read multiple transac-
tions, the bits select whether to read to a cache line boundary or to fill the prefetch buffer. In all cases, if the
bits are selected to fill the prefetch buffer, the maximum amount of data that is requested on the target inter-
face is controllable by the setting of the maximum memory read byte count bits of the Primary and Secondary
Data Buffering Control registers. When more than 512 bytes are requested, the bridge fetches data to fill the
buffer and then fetches more data to keep the buffer filled as sectors (128 bytes) are emptied and become
free to use again.
相关PDF资料 |
PDF描述 |
|---|---|
| IBM25403GCX-3JC76C2 | RISC PROCESSOR, PQFP16 |
| IBM25405GP-3BA200C2 | RISC PROCESSOR, PBGA456 |
| IBM25EMPPC603EFG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| IBM25EMPPC603EBG-100 | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| IBM25EMPPC740LDBC4000 | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IBM24L5086 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM25403GCX-3BC80C2 | 制造商:IBM 功能描述:RISC PROCESSOR, 160 Pin Plastic BGA |
| IBM25403GCX-3JC50C2 | 制造商:IBM 功能描述:403GCX-3JC50C2 |
| IBM25403GCX-3JC66C2 | 制造商:IBM 功能描述: |
| IBM25403GCX3JC76C2 | 制造商:IBM 功能描述: |
发布紧急采购，3分钟左右您将得到回复。