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参数资料
| 型号： | IBM21P100BGC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA304 |
| 封装： | 31 X 31 MM, PLASTIC, BGA-304 |
| 文件页数： | 35/144页 |
| 文件大小： | 5197K |
| 代理商： | IBM21P100BGC |
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IBM21P100BGC
IBM 133 PCI-X Bridge R2.0
ppb20_preface.fm.01
October 15, 2001
Preface
Page 13 of 144
Destination Bus
For transactions that cross the bridge, the destination bus is the bus on which the
the completer of a transaction resides.
Downstream
Transactions forwarded from the primary interface to the secondary interface are
referred to as flowing downstream, regardless of the direction of the data flow.
Originating Bus
For transactions that cross the bridge, the originating bus is the bus on which the
initiator of a transaction resides.
Parity
Throughout this specification,
odd parity should be interpreted as the total number
of bits with a b‘1’ valuewithina field and thefield’s associated parity bit is an odd
number. Similarly,
even parity should be interpreted as the total number of bits with
ab‘1’ value within a field and the field’s associated parity bit is an even number.
Primary Interface
The interface connected to the bus closest to the Host Processor.
Reserved Bits
The term ‘reserved’ is applied to any undefined, unimplemented, or spare bits within
the registers of the device. No assumptions may be made about these bits in any
way, as these bits may have meaning assigned to them in the future. Care must be
taken when accessing registers with reserved bit fields. For read accesses, such
bits should not be expected to have any specific or consistent value and appro-
priate masks should be used to extract only those bits that are defined. For write
accesses, the values of reserved bit fields should be preserved by performing a
read-modify-write sequence.
Secondary Interface
The interface connected to the bus farthest from the Host Processor.
Upstream
Transactions forwarded from the secondary interface to the primary interface are
referred to as flowing upstream, regardless of the direction of the data flow.
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